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refactor(cam): extract match engine into separate module and centralize parameters

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- Split cam_core into pure memory (cam_core.sv) and match engine (match_engine.sv)
- Add cam_params.svh with centralized parameter definitions (NUM_ROWS, HASH_BITS, LANES, etc.)
- Update cam_top.sv to use shared parameters and compose match_engine
- Update Makefile to include new match_engine module and correct Verilator define syntax
This commit is contained in:
SikongJueluo
2026-05-02 22:49:57 +08:00
parent f71bf06484
commit f5daaa2667
5 changed files with 302 additions and 236 deletions
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7
hw/sim/Makefile
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@@ -14,17 +14,20 @@ NUM_ROWS ?= 512
HASH_BITS ?= 512
LANES ?= 16
EXTRA_ARGS += -DNUM_ROWS=$(NUM_ROWS) -DHASH_BITS=$(HASH_BITS) -DLANES=$(LANES)
EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
# cocotb passes PLUSARGS/EXTRA_ARGS differently across simulators. Keep
# SystemVerilog parameters explicit through COMPILE_ARGS for Verilator.
COMPILE_ARGS += -Wall -Wno-fatal
COMPILE_ARGS += -I$(PWD)/../rtl
COMPILE_ARGS += +define+SIM_DEBUG
COMPILE_ARGS += $(EXTRA_DEFINES)
VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv
include $(shell cocotb-config --makefiles)/Makefile.sim
include $(shell uv run cocotb-config --makefiles)/Makefile.sim