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https://github.com/SikongJueluo/Mini-Nav.git
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refactor(cam): extract match engine into separate module and centralize parameters
- Split cam_core into pure memory (cam_core.sv) and match engine (match_engine.sv) - Add cam_params.svh with centralized parameter definitions (NUM_ROWS, HASH_BITS, LANES, etc.) - Update cam_top.sv to use shared parameters and compose match_engine - Update Makefile to include new match_engine module and correct Verilator define syntax
This commit is contained in:
191
hw/rtl/match_engine.sv
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191
hw/rtl/match_engine.sv
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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module match_engine (
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input logic clk,
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input logic rst_n,
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// Query interface
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input logic query_valid,
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output logic query_ready,
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input logic [(`HASH_BITS)-1:0] query_hash,
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output logic result_valid,
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input logic result_ready,
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output logic [(`ROW_BITS)-1:0] result_row,
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output logic [(`SCORE_BITS)-1:0] result_score,
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output logic busy,
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// To/from cam_core
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output logic [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
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input logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
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`ifdef SIM_NOISE
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,input logic [(`LANES)*(`HASH_BITS)-1:0] noise_mask_lanes_flat
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`endif
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`ifdef SIM_DEBUG
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,output logic [(`NUM_ROWS)*(`SCORE_BITS)-1:0] score_debug_flat
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`endif
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);
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typedef enum logic [1:0] { // state_t
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S_IDLE, // Waiting for query_valid
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S_SCAN, // Scanning rows in LANES-wide batches
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S_DONE // Result ready, waiting for result_ready
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} state_t;
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state_t state_q, state_d;
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logic [(`HASH_BITS)-1:0] query_q;
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logic [(`ROW_BITS)-1:0] base_row_q, base_row_d;
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logic [(`ROW_BITS)-1:0] prev_best_idx [0:(`LANES)];
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logic [(`ROW_BITS)-1:0] next_best_idx [0:(`LANES)-1];
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logic [(`SCORE_BITS)-1:0] prev_best_score [0:(`LANES)];
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logic [(`SCORE_BITS)-1:0] next_best_score [0:(`LANES)-1];
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logic [(`SCORE_BITS)-1:0] lane_score [0:(`LANES)-1];
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logic [(`ROW_BITS)-1:0] lane_row [0:(`LANES)-1];
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logic lane_valid [0:(`LANES)-1];
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logic [(`ROW_BITS)-1:0] batch_best_idx;
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logic [(`SCORE_BITS)-1:0] batch_best_score;
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logic [(`ROW_BITS)-1:0] best_idx_q, best_idx_d;
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logic [(`SCORE_BITS)-1:0] best_score_q, best_score_d;
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assign query_ready = (state_q == S_IDLE);
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assign result_valid = (state_q == S_DONE);
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assign result_row = best_idx_q;
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assign result_score = best_score_q;
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assign busy = (state_q == S_SCAN);
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genvar lane;
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generate
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for (lane = 0; lane < `LANES; lane++) begin : gen_lanes
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logic [(`HASH_BITS)-1:0] row_hash;
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logic [(`HASH_BITS)-1:0] effective_hash;
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logic [(`HASH_BITS)-1:0] match_bits;
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assign lane_row[lane] = base_row_q + lane[(`ROW_BITS)-1:0];
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assign lane_valid[lane] = (lane_row[lane] < `NUM_ROWS);
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assign rd_addr_lanes_flat[lane*`ROW_BITS +: `ROW_BITS] = lane_row[lane];
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assign row_hash = rd_hash_lanes_flat[lane*`HASH_BITS +: `HASH_BITS];
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`ifdef SIM_NOISE
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assign effective_hash = row_hash ^ noise_mask_lanes_flat[lane*`HASH_BITS +: `HASH_BITS];
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`else
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assign effective_hash = row_hash;
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`endif
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assign match_bits = ~(query_q ^ effective_hash);
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popcount #(
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.WIDTH(`HASH_BITS),
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.GROUP(8),
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.OUT_WIDTH(`SCORE_BITS)
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) u_popcount (
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.bits_i(match_bits),
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.count_o(lane_score[lane])
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);
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argmax_update #(
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.ROW_BITS(`ROW_BITS),
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.SCORE_BITS(`SCORE_BITS)
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) u_argmax_update (
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.best_index_i(prev_best_idx[lane]),
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.best_score_i(prev_best_score[lane]),
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.cand_index_i(lane_row[lane]),
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.cand_score_i(lane_valid[lane] ? lane_score[lane] : '0),
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.best_index_o(next_best_idx[lane]),
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.best_score_o(next_best_score[lane])
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);
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end
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endgenerate
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// Initialize chain with current batch seed
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assign prev_best_idx[0] = best_idx_q;
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assign prev_best_score[0] = best_score_q;
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// Propagate per-lane results
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for (genvar l = 0; l < `LANES; l++) begin : chain_link
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assign prev_best_idx[l+1] = next_best_idx[l];
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assign prev_best_score[l+1] = next_best_score[l];
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end
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assign batch_best_idx = prev_best_idx[`LANES];
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assign batch_best_score = prev_best_score[`LANES];
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always_comb begin
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state_d = state_q;
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base_row_d = base_row_q;
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best_idx_d = best_idx_q;
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best_score_d = best_score_q;
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unique case (state_q)
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S_IDLE: begin
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if (query_valid) begin
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state_d = S_SCAN;
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base_row_d = '0;
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best_idx_d = TIE_BREAK_SENTINEL; // Lower index wins tie-break
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best_score_d = '0;
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end
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end
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S_SCAN: begin
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best_idx_d = batch_best_idx;
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best_score_d = batch_best_score;
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if (base_row_q + `LANES >= `NUM_ROWS) begin
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state_d = S_DONE;
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end else begin
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base_row_d = base_row_q + `LANES;
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end
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end
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S_DONE: begin
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if (result_ready) begin
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state_d = S_IDLE;
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end
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end
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default: begin
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state_d = S_IDLE;
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end
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endcase
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_q <= S_IDLE;
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query_q <= '0;
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base_row_q <= '0;
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best_idx_q <= '0;
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best_score_q <= '0;
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end else begin
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state_q <= state_d;
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base_row_q <= base_row_d;
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best_idx_q <= best_idx_d;
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best_score_q <= best_score_d;
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if ((state_q == S_IDLE) && query_valid) begin
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query_q <= query_hash;
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end
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`ifdef SIM_DEBUG
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if (state_q == S_IDLE && query_valid) begin
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score_debug_flat <= '0;
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end else if (state_q == S_SCAN) begin
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for (int l = 0; l < `LANES; l++) begin
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if (lane_valid[l]) begin
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score_debug_flat[lane_row[l]*`SCORE_BITS +: `SCORE_BITS] <= lane_score[l];
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end
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end
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end
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`endif
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end
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end
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`ifdef SIM_DEBUG
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initial begin
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score_debug_flat = '0;
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end
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`endif
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endmodule
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