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feat(hw/rtl): implement full Top-K CAM search pipeline with serial result output

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- add TOPK_K, FIFO_DEPTH, RESULT_SERIAL parameters to cam_params
- add candidate_fifo: synchronous ready/valid FIFO for (row, score) candidates
- add topk_tracker: tracks top-K candidates with clear/ready handshake
- add result_serializer: serializes packed Top-K array into rank-ordered stream
- refactor match_engine_pipeline from 4-state to 8-state Top-K pipeline
- extend cam_top with serial Top-K interface (result_rank/row/score/last)
- add backward-compatible top1_index/top1_score aliases from rank-0 beat
- add comprehensive tests for all new modules
This commit is contained in:
SikongJueluo
2026-05-19 18:19:05 +08:00
parent 8bcad1f23f
commit e4cbb5e30d
21 changed files with 2152 additions and 124 deletions
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3
hw/syn/synth_cam_top_flat.ys
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@@ -15,6 +15,9 @@ read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/candidate_fifo.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/topk_tracker.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/result_serializer.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv