feat(hw/rtl): implement full Top-K CAM search pipeline with serial result output

- add TOPK_K, FIFO_DEPTH, RESULT_SERIAL parameters to cam_params
- add candidate_fifo: synchronous ready/valid FIFO for (row, score) candidates
- add topk_tracker: tracks top-K candidates with clear/ready handshake
- add result_serializer: serializes packed Top-K array into rank-ordered stream
- refactor match_engine_pipeline from 4-state to 8-state Top-K pipeline
- extend cam_top with serial Top-K interface (result_rank/row/score/last)
- add backward-compatible top1_index/top1_score aliases from rank-0 beat
- add comprehensive tests for all new modules

hw/syn/Makefile

@@ -16,6 +16,8 @@ TOP      ?= cam_top
 NUM_ROWS ?= 4096
 HASH_BITS ?= 512
 LANES    ?= 8
+TOPK_K   ?= 4
+FIFO_DEPTH ?= 16
 OUT_DIR  ?= build
 
 # ── TOP enforcement (only cam_top is supported) ───────────────────────────────
@@ -41,7 +43,7 @@ ARTIFACTS := $(HIER_JSON) $(FLAT_JSON) $(SYNTH_V) $(HIER_LOG) $(FLAT_LOG)
 # ── Yosys command-line defines (always passed) ────────────────────────────────
 # cam_params.svh uses `ifndef guards, so -D on the Yosys CLI overrides defaults.
 # Use -D NAME=value syntax (Yosys 0.62); do NOT use -define.
-YOSYS_DEFINES := -D NUM_ROWS=$(NUM_ROWS) -D HASH_BITS=$(HASH_BITS) -D LANES=$(LANES)
+YOSYS_DEFINES := -D NUM_ROWS=$(NUM_ROWS) -D HASH_BITS=$(HASH_BITS) -D LANES=$(LANES) -D TOPK_K=$(TOPK_K) -D FIFO_DEPTH=$(FIFO_DEPTH)
 
 # ── Targets ───────────────────────────────────────────────────────────────────
 .PHONY: synth hier flat clean

hw/syn/synth_cam_top_flat.ys

@@ -15,6 +15,9 @@ read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
 read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
 read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
 read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
+read_verilog -sv -D SYNTHESIS ../rtl/core/candidate_fifo.sv
+read_verilog -sv -D SYNTHESIS ../rtl/core/topk_tracker.sv
+read_verilog -sv -D SYNTHESIS ../rtl/core/result_serializer.sv
 read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
 read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
 read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv

hw/syn/synth_cam_top_hier.ys

@@ -15,6 +15,9 @@ read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
 read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
 read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
 read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
+read_verilog -sv -D SYNTHESIS ../rtl/core/candidate_fifo.sv
+read_verilog -sv -D SYNTHESIS ../rtl/core/topk_tracker.sv
+read_verilog -sv -D SYNTHESIS ../rtl/core/result_serializer.sv
 read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
 read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
 read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv