From e1a34d6540ae7b064bf1f6703801c81d0b8bcf74 Mon Sep 17 00:00:00 2001 From: SikongJueluo Date: Wed, 13 May 2026 19:08:06 +0800 Subject: [PATCH] refactor!: remove legacy match_engine and related CAM modules - Delete popcount.sv, argmax_update.sv, cam_core.sv, match_engine.sv - Remove obsolete VERILOG_SOURCES entries from Makefile - Update comment in cam_top.sv to reference match_engine_pipeline - Add verilator to devenv.nix for simulation support --- devenv.nix | 1 + hw/rtl/argmax_update.sv | 26 ------ hw/rtl/cam_core.sv | 32 ------- hw/rtl/cam_top.sv | 4 +- hw/rtl/match_engine.sv | 184 ---------------------------------------- hw/rtl/popcount.sv | 41 --------- hw/sim/Makefile | 4 - 7 files changed, 3 insertions(+), 289 deletions(-) delete mode 100644 hw/rtl/argmax_update.sv delete mode 100644 hw/rtl/cam_core.sv delete mode 100644 hw/rtl/match_engine.sv delete mode 100644 hw/rtl/popcount.sv diff --git a/devenv.nix b/devenv.nix index 9319f98..21671b2 100644 --- a/devenv.nix +++ b/devenv.nix @@ -17,6 +17,7 @@ in { packages = with pkgs; [ nil + verilator ]; enterShell = '' diff --git a/hw/rtl/argmax_update.sv b/hw/rtl/argmax_update.sv deleted file mode 100644 index eaddfcf..0000000 --- a/hw/rtl/argmax_update.sv +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps - -module argmax_update #( - parameter int ROW_BITS = 9, - parameter int SCORE_BITS = 10 -) ( - input logic [ROW_BITS-1:0] best_index_i, - input logic [SCORE_BITS-1:0] best_score_i, - - input logic [ROW_BITS-1:0] cand_index_i, - input logic [SCORE_BITS-1:0] cand_score_i, - - output logic [ROW_BITS-1:0] best_index_o, - output logic [SCORE_BITS-1:0] best_score_o -); - always_comb begin - best_index_o = best_index_i; - best_score_o = best_score_i; - - if ((cand_score_i > best_score_i) || - ((cand_score_i == best_score_i) && (cand_index_i < best_index_i))) begin - best_index_o = cand_index_i; - best_score_o = cand_score_i; - end - end -endmodule diff --git a/hw/rtl/cam_core.sv b/hw/rtl/cam_core.sv deleted file mode 100644 index 5d547c6..0000000 --- a/hw/rtl/cam_core.sv +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -`include "cam_params.svh" - -module cam_core ( - input logic clk, - input logic rst_n, - input logic wr_en, - input logic [(`ROW_BITS)-1:0] wr_row, - input logic [(`HASH_BITS)-1:0] wr_hash, - input logic [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat, - output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat -); - - logic [(`HASH_BITS)-1:0] cam_mem[0:(`NUM_ROWS)-1]; - - // Memory write path. - always_ff @(posedge clk) begin - if (wr_en) begin - cam_mem[wr_row] <= wr_hash; - end - end - - // Per-lane combinational read. - genvar l; - generate - for (l = 0; l < `LANES; l++) begin : rd_lane - assign rd_hash_lanes_flat[l*`HASH_BITS +: `HASH_BITS] = - cam_mem[rd_addr_lanes_flat[l*`ROW_BITS +: `ROW_BITS]]; - end - endgenerate - -endmodule diff --git a/hw/rtl/cam_top.sv b/hw/rtl/cam_top.sv index 0e19a2a..c195c0b 100644 --- a/hw/rtl/cam_top.sv +++ b/hw/rtl/cam_top.sv @@ -42,8 +42,8 @@ module cam_top #( // ── Internal signals ── logic storage_wr_ready; // cam_noisy write-side ready - logic match_query_ready; // match_engine idle - logic match_busy; // match_engine scanning/result pending + logic match_query_ready; // match_engine_pipeline idle + logic match_busy; // match_engine_pipeline scanning/result pending // ── Internal valid forwarding ── logic storage_wr_valid; diff --git a/hw/rtl/match_engine.sv b/hw/rtl/match_engine.sv deleted file mode 100644 index 871c949..0000000 --- a/hw/rtl/match_engine.sv +++ /dev/null @@ -1,184 +0,0 @@ -`timescale 1ns / 1ps -`include "cam_params.svh" - -module match_engine ( - input logic clk, - input logic rst_n, - // Query interface - input logic query_valid, - output logic query_ready, - input logic [(`HASH_BITS)-1:0] query_hash, - output logic result_valid, - input logic result_ready, - output logic [(`ROW_BITS)-1:0] result_row, - output logic [(`SCORE_BITS)-1:0] result_score, - output logic busy, - // To/from cam_core - output logic [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat, - input logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat -`ifdef SIM_DEBUG - ,output logic [(`NUM_ROWS)*(`SCORE_BITS)-1:0] score_debug_flat -`endif -); - - typedef enum logic [1:0] { // state_t - S_IDLE, // Waiting for query_valid - S_SCAN, // Scanning rows in LANES-wide batches - S_DONE // Result ready, waiting for result_ready - } state_t; - - state_t state_q, state_d; - logic [(`HASH_BITS)-1:0] query_q; - logic [(`ROW_BITS)-1:0] base_row_q, base_row_d; - - logic [(`ROW_BITS)-1:0] prev_best_idx [0:(`LANES)]; - logic [(`ROW_BITS)-1:0] next_best_idx [0:(`LANES)-1]; - logic [(`SCORE_BITS)-1:0] prev_best_score [0:(`LANES)]; - logic [(`SCORE_BITS)-1:0] next_best_score [0:(`LANES)-1]; - - logic [(`SCORE_BITS)-1:0] lane_score [0:(`LANES)-1]; - logic [(`ROW_BITS)-1:0] lane_row [0:(`LANES)-1]; - logic lane_valid [0:(`LANES)-1]; - - logic [(`ROW_BITS)-1:0] batch_best_idx; - logic [(`SCORE_BITS)-1:0] batch_best_score; - - logic [(`ROW_BITS)-1:0] best_idx_q, best_idx_d; - logic [(`SCORE_BITS)-1:0] best_score_q, best_score_d; - - assign query_ready = (state_q == S_IDLE); - assign result_valid = (state_q == S_DONE); - assign result_row = best_idx_q; - assign result_score = best_score_q; - assign busy = (state_q == S_SCAN); - - genvar lane; - generate - for (lane = 0; lane < `LANES; lane++) begin : gen_lanes - logic [(`HASH_BITS)-1:0] row_hash; - logic [(`HASH_BITS)-1:0] effective_hash; - logic [(`HASH_BITS)-1:0] match_bits; - - assign lane_row[lane] = base_row_q + lane[(`ROW_BITS)-1:0]; - assign lane_valid[lane] = (lane_row[lane] < `NUM_ROWS); - - assign rd_addr_lanes_flat[lane*`ROW_BITS +: `ROW_BITS] = lane_row[lane]; - assign row_hash = rd_hash_lanes_flat[lane*`HASH_BITS +: `HASH_BITS]; - - assign effective_hash = row_hash; - - assign match_bits = ~(query_q ^ effective_hash); - - popcount #( - .WIDTH(`HASH_BITS), - .GROUP(8), - .OUT_WIDTH(`SCORE_BITS) - ) u_popcount ( - .bits_i(match_bits), - .count_o(lane_score[lane]) - ); - - argmax_update #( - .ROW_BITS(`ROW_BITS), - .SCORE_BITS(`SCORE_BITS) - ) u_argmax_update ( - .best_index_i(prev_best_idx[lane]), - .best_score_i(prev_best_score[lane]), - .cand_index_i(lane_row[lane]), - .cand_score_i(lane_valid[lane] ? lane_score[lane] : '0), - .best_index_o(next_best_idx[lane]), - .best_score_o(next_best_score[lane]) - ); - end - endgenerate - - // Initialize chain with current batch seed - assign prev_best_idx[0] = best_idx_q; - assign prev_best_score[0] = best_score_q; - - // Propagate per-lane results - for (genvar l = 0; l < `LANES; l++) begin : chain_link - assign prev_best_idx[l+1] = next_best_idx[l]; - assign prev_best_score[l+1] = next_best_score[l]; - end - - assign batch_best_idx = prev_best_idx[`LANES]; - assign batch_best_score = prev_best_score[`LANES]; - - always_comb begin - state_d = state_q; - base_row_d = base_row_q; - best_idx_d = best_idx_q; - best_score_d = best_score_q; - - unique case (state_q) - S_IDLE: begin - if (query_valid) begin - state_d = S_SCAN; - base_row_d = '0; - best_idx_d = TIE_BREAK_SENTINEL; // Lower index wins tie-break - best_score_d = '0; - end - end - - S_SCAN: begin - best_idx_d = batch_best_idx; - best_score_d = batch_best_score; - - if (base_row_q + `LANES >= `NUM_ROWS) begin - state_d = S_DONE; - end else begin - base_row_d = base_row_q + `LANES; - end - end - - S_DONE: begin - if (result_ready) begin - state_d = S_IDLE; - end - end - - default: begin - state_d = S_IDLE; - end - endcase - end - - always_ff @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - state_q <= S_IDLE; - query_q <= '0; - base_row_q <= '0; - best_idx_q <= '0; - best_score_q <= '0; - end else begin - state_q <= state_d; - base_row_q <= base_row_d; - best_idx_q <= best_idx_d; - best_score_q <= best_score_d; - - if ((state_q == S_IDLE) && query_valid) begin - query_q <= query_hash; - end - -`ifdef SIM_DEBUG - if (state_q == S_IDLE && query_valid) begin - score_debug_flat <= '0; - end else if (state_q == S_SCAN) begin - for (int l = 0; l < `LANES; l++) begin - if (lane_valid[l]) begin - score_debug_flat[lane_row[l]*`SCORE_BITS +: `SCORE_BITS] <= lane_score[l]; - end - end - end -`endif - end - end - -`ifdef SIM_DEBUG - initial begin - score_debug_flat = '0; - end -`endif - -endmodule diff --git a/hw/rtl/popcount.sv b/hw/rtl/popcount.sv deleted file mode 100644 index fdc3273..0000000 --- a/hw/rtl/popcount.sv +++ /dev/null @@ -1,41 +0,0 @@ -`timescale 1ns/1ps - -module popcount #( - parameter int WIDTH = 512, - parameter int GROUP = 8, - parameter int OUT_WIDTH = $clog2(WIDTH + 1) -) ( - input logic [WIDTH-1:0] bits_i, - output logic [OUT_WIDTH-1:0] count_o -); - localparam int NUM_GROUPS = (WIDTH + GROUP - 1) / GROUP; - localparam int GROUP_COUNT_WIDTH = $clog2(GROUP + 1); - - logic [GROUP_COUNT_WIDTH-1:0] group_counts [NUM_GROUPS]; - - genvar g; - generate - for (g = 0; g < NUM_GROUPS; g++) begin : gen_group_popcount - always_comb begin - group_counts[g] = '0; - for (int b = 0; b < GROUP; b++) begin - int idx; - idx = g * GROUP + b; - if (idx < WIDTH) begin - group_counts[g] = group_counts[g] + bits_i[idx]; - end - end - end - end - endgenerate - - // Reduction over small group counts. This is intentionally simple and - // synthesis-friendly enough for the first prototype. If timing fails, - // replace this block with a fully staged adder tree. - always_comb begin - count_o = '0; - for (int i = 0; i < NUM_GROUPS; i++) begin - count_o = count_o + group_counts[i]; - end - end -endmodule diff --git a/hw/sim/Makefile b/hw/sim/Makefile index 7192c40..ef139df 100644 --- a/hw/sim/Makefile +++ b/hw/sim/Makefile @@ -65,9 +65,6 @@ COMPILE_ARGS += -Wno-WIDTHEXPAND COMPILE_ARGS += -Wno-UNOPTFLAT endif -VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv -VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv -VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv VERILOG_SOURCES += $(PWD)/../rtl/random/random128.sv VERILOG_SOURCES += $(PWD)/../rtl/noise_mask_grouped.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_core_banked.sv @@ -76,7 +73,6 @@ VERILOG_SOURCES += $(PWD)/../rtl/cam_read_noise.sv VERILOG_SOURCES += $(PWD)/../rtl/popcount_pipeline.sv VERILOG_SOURCES += $(PWD)/../rtl/match_engine_pipeline.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv -VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv include $(shell uv run cocotb-config --makefiles)/Makefile.sim