feat(cam): migrate noise generation from xorshift64 to xorshift128

- Replace NOISE_GEN_BITS/NOISE_SAMPLE_BITS parameters with unified NOISE_BITS
- Use xorshift128 (random128) instead of xorshift64 for PRNG
- Add flip_mask_next combinational helper for single-cycle mask computation
- Add random_enable signal to advance PRNG only on accepted noisy writes
- Simplify FSM by removing mask_group_idx counter
- Update parameter validation: GROUP_BITS (= HASH_BITS/NOISE_BITS) must equal 64
- Update ref_model.py and tests to match new seed convention: {seed, seed}
- Update Makefile and sweep_noise.py with renamed parameters

hw/sim/Makefile

@@ -13,10 +13,10 @@ LANES ?= 16
 NOISE_EN          ?= 1
 NOISE_RATE_NUM    ?= 1
 NOISE_RATE_DEN    ?= 100
-NOISE_GEN_BITS    ?= 8
-NOISE_SAMPLE_BITS ?= 8
+NOISE_BITS        ?= 8
 # NOISE_SEED cannot be overridden via Makefile due to Verilator -G quoting issues
-# with 64'h hex literals. To change the seed, edit the default in cam_noisy.sv.
+# with 64'h hex literals. To change the seed, edit the default in cam_top.sv
+# (sim top is cam_top, which passes it to cam_noisy).
 
 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
 
@@ -29,8 +29,7 @@ COMPILE_ARGS += $(EXTRA_DEFINES)
 COMPILE_ARGS += -GNOISE_EN=$(NOISE_EN)
 COMPILE_ARGS += -GNOISE_RATE_NUM=$(NOISE_RATE_NUM)
 COMPILE_ARGS += -GNOISE_RATE_DEN=$(NOISE_RATE_DEN)
-COMPILE_ARGS += -GNOISE_GEN_BITS=$(NOISE_GEN_BITS)
-COMPILE_ARGS += -GNOISE_SAMPLE_BITS=$(NOISE_SAMPLE_BITS)
+COMPILE_ARGS += -GNOISE_BITS=$(NOISE_BITS)
 
 # Cleaner terminal output
 export QUIET ?= 1
@@ -48,6 +47,7 @@ endif
 VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
 VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
+VERILOG_SOURCES += $(PWD)/../rtl/random/random128.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv
 VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv