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feat(cam): migrate noise generation from xorshift64 to xorshift128

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- Replace NOISE_GEN_BITS/NOISE_SAMPLE_BITS parameters with unified NOISE_BITS
- Use xorshift128 (random128) instead of xorshift64 for PRNG
- Add flip_mask_next combinational helper for single-cycle mask computation
- Add random_enable signal to advance PRNG only on accepted noisy writes
- Simplify FSM by removing mask_group_idx counter
- Update parameter validation: GROUP_BITS (= HASH_BITS/NOISE_BITS) must equal 64
- Update ref_model.py and tests to match new seed convention: {seed, seed}
- Update Makefile and sweep_noise.py with renamed parameters
This commit is contained in:
SikongJueluo
2026-05-05 19:30:51 +08:00
parent 0dd01fb1b7
commit cbafc4524e
8 changed files with 178 additions and 152 deletions
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156
hw/rtl/cam_noisy.sv
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@@ -2,46 +2,59 @@
`include "cam_params.svh"
// Design constraints:
// HASH_BITS % NOISE_GEN_BITS == 0
// NOISE_GEN_BITS * NOISE_SAMPLE_BITS == 64
// HASH_BITS % NOISE_BITS == 0
// GROUP_BITS (= HASH_BITS / NOISE_BITS) == 64 (needed for 6-bit index)
// NOISE_BITS * GROUP_RAND_BITS <= 128
// 0 <= NOISE_RATE_NUM <= NOISE_RATE_DEN
// NOISE_RATE_DEN > 0
// NOISE_SEED != 64'd0
// NOISE_BITS > 0
module cam_noisy #(
parameter bit NOISE_EN = 1'b1,
parameter int NOISE_RATE_NUM = 1,
parameter int NOISE_RATE_DEN = 100,
parameter int NOISE_GEN_BITS = 8,
parameter int NOISE_SAMPLE_BITS = 8,
parameter logic [63:0] NOISE_SEED = 64'hB504_F32D_B504_F32D
parameter bit NOISE_EN = 1'b1,
parameter int NOISE_RATE_NUM = 70,
parameter int NOISE_RATE_DEN = 100,
parameter logic [63:0] NOISE_SEED = 64'hB504_F32D_B504_F32D,
parameter int NOISE_BITS = 8
) (
input logic clk,
input logic rst_n,
input logic clk,
input logic rst_n,
// Write interface (handshake)
input logic wr_valid,
output logic wr_ready,
input logic [(`ROW_BITS)-1:0] wr_addr,
input logic [(`HASH_BITS)-1:0] write_hash,
input logic wr_valid,
output logic wr_ready,
input logic [ (`ROW_BITS)-1:0] wr_addr,
input logic [(`HASH_BITS)-1:0] write_hash,
// Read interface (passthrough to cam_core, combinational read)
input logic [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
input logic [ (`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
);
// ── Local parameters ──
localparam int GROUP_BITS = `HASH_BITS / NOISE_BITS;
localparam int BIT_INDEX_BITS = 6;
localparam int SAMPLE_BITS = 8;
localparam int GROUP_RAND_BITS = BIT_INDEX_BITS + SAMPLE_BITS; // 14
localparam int SAMPLE_RANGE = 2 ** SAMPLE_BITS; // 256
localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
// ── Elaboration-time parameter checks ──
initial begin
if (`HASH_BITS % NOISE_GEN_BITS != 0)
$fatal(1, "HASH_BITS (%0d) must be divisible by NOISE_GEN_BITS (%0d)", `HASH_BITS, NOISE_GEN_BITS);
if (NOISE_GEN_BITS * NOISE_SAMPLE_BITS != 64)
$fatal(1, "NOISE_GEN_BITS*NOISE_SAMPLE_BITS must equal 64, got %0d", NOISE_GEN_BITS * NOISE_SAMPLE_BITS);
if (NOISE_BITS <= 0)
$fatal(1, "NOISE_BITS must be > 0, got %0d", NOISE_BITS);
if (`HASH_BITS % NOISE_BITS != 0)
$fatal(1, "HASH_BITS (%0d) must be divisible by NOISE_BITS (%0d)", `HASH_BITS, NOISE_BITS);
if (GROUP_BITS != 64)
$fatal(1, "GROUP_BITS (= HASH_BITS/NOISE_BITS) must equal 64 for 6-bit index, got %0d", GROUP_BITS);
if (NOISE_BITS * GROUP_RAND_BITS > 128)
$fatal(1, "NOISE_BITS*GROUP_RAND_BITS must be <= 128, got %0d", NOISE_BITS * GROUP_RAND_BITS);
if (NOISE_RATE_DEN <= 0)
$fatal(1, "NOISE_RATE_DEN must be > 0, got %0d", NOISE_RATE_DEN);
if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN)
$fatal(1, "NOISE_RATE_NUM (%0d) must be in [0, NOISE_RATE_DEN=%0d]", NOISE_RATE_NUM, NOISE_RATE_DEN);
if (NOISE_SEED == 64'd0)
$fatal(1, "NOISE_SEED must be nonzero — xorshift64 with zero seed never advances");
$fatal(1, "NOISE_SEED must be nonzero — xorshift128/random128 with zero seed never advances");
end
// ── FSM states ──
@@ -58,24 +71,20 @@ module cam_noisy #(
logic [(`HASH_BITS)-1:0] write_hash_q;
// ── Noise generation ──
logic [63:0] prng_state;
logic [(`HASH_BITS)-1:0] flip_mask;
localparam int MASK_GROUPS = `HASH_BITS / NOISE_GEN_BITS;
logic [($clog2(`HASH_BITS/NOISE_GEN_BITS+1))-1:0] mask_group_idx; // 0..HASH_BITS/NOISE_GEN_BITS-1
logic [127:0] random_num;
// ── Precomputed threshold ──
localparam int SAMPLE_RANGE = 1 << NOISE_SAMPLE_BITS;
localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
// ── xorshift64 PRNG function ──
function automatic logic [63:0] xorshift64(input logic [63:0] x);
logic [63:0] s;
s = x;
s ^= s << 13;
s ^= s >> 7;
s ^= s << 17;
return s;
endfunction
// ── Combinational next-mask helper ──
// Computes flip_mask_next from fresh random_num in one cycle.
logic [(`HASH_BITS)-1:0] flip_mask_next;
always_comb begin
flip_mask_next = '0;
for (int i = 0; i < NOISE_BITS; i++) begin
if (random_num[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
flip_mask_next[i * GROUP_BITS + random_num[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
end
end
end
// ── Noisy hash for cam_core write ──
logic [(`HASH_BITS)-1:0] noisy_hash;
@@ -84,6 +93,10 @@ module cam_noisy #(
// ── wr_ready: only in IDLE ──
assign wr_ready = (curr_state == S_IDLE);
// ── random128 enable: advance random on accepted noisy write ──
logic random_enable;
assign random_enable = wr_ready && wr_valid && NOISE_EN && (NOISE_RATE_NUM > 0);
// ── FSM block 1: state register ──
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
@@ -99,16 +112,13 @@ module cam_noisy #(
case (curr_state)
S_IDLE: begin
if (wr_valid && wr_ready) begin
if (NOISE_EN && (NOISE_RATE_NUM > 0))
next_state = S_GEN_MASK;
else
next_state = S_COMMIT;
if (NOISE_EN && (NOISE_RATE_NUM > 0)) next_state = S_GEN_MASK;
else next_state = S_COMMIT;
end
end
S_GEN_MASK: begin
if (int'(mask_group_idx) == (MASK_GROUPS - 1))
next_state = S_COMMIT;
next_state = S_COMMIT;
end
S_COMMIT: begin
@@ -122,17 +132,13 @@ module cam_noisy #(
// ── FSM block 3: state actions / datapath registers ──
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
addr_q <= '0;
write_hash_q <= '0;
flip_mask <= '0;
prng_state <= NOISE_SEED;
mask_group_idx <= '0;
addr_q <= '0;
write_hash_q <= '0;
flip_mask <= '0;
end else begin
case (curr_state)
S_IDLE: begin
flip_mask <= '0;
mask_group_idx <= '0;
flip_mask <= '0;
if (wr_valid && wr_ready) begin
addr_q <= wr_addr;
write_hash_q <= write_hash;
@@ -140,36 +146,21 @@ module cam_noisy #(
end
S_GEN_MASK: begin
// Advance PRNG — sample from NEW state to match ref_model
logic [63:0] prng_next;
prng_next = xorshift64(prng_state);
prng_state <= prng_next;
// Generate NOISE_GEN_BITS flip decisions from 64-bit PRNG output
for (int b = 0; b < NOISE_GEN_BITS; b++) begin
logic [NOISE_SAMPLE_BITS-1:0] sample;
sample = prng_next[b * NOISE_SAMPLE_BITS +: NOISE_SAMPLE_BITS];
if (int'(sample) < THRESHOLD) begin
flip_mask[mask_group_idx * NOISE_GEN_BITS + b] <= 1'b1;
end
end
mask_group_idx <= mask_group_idx + 1;
flip_mask <= flip_mask_next;
end
S_COMMIT: begin
// Write noisy hash to cam_core (one cycle)
// cam_core.wr_en is asserted here via comb assign below
// Write happens via combinational core_wr_en
end
default: ; // No-op
default: ; // No-op
endcase
end
end
// ── cam_core instance ──
logic core_wr_en;
logic [(`ROW_BITS)-1:0] core_wr_row;
logic core_wr_en;
logic [ (`ROW_BITS)-1:0] core_wr_row;
logic [(`HASH_BITS)-1:0] core_wr_hash;
assign core_wr_en = (curr_state == S_COMMIT);
@@ -177,13 +168,22 @@ module cam_noisy #(
assign core_wr_hash = noisy_hash;
cam_core u_core (
.clk (clk),
.rst_n (rst_n),
.wr_en (core_wr_en),
.wr_row (core_wr_row),
.wr_hash (core_wr_hash),
.rd_addr_lanes_flat (rd_addr_lanes_flat),
.rd_hash_lanes_flat (rd_hash_lanes_flat)
.clk (clk),
.rst_n (rst_n),
.wr_en (core_wr_en),
.wr_row (core_wr_row),
.wr_hash (core_wr_hash),
.rd_addr_lanes_flat(rd_addr_lanes_flat),
.rd_hash_lanes_flat(rd_hash_lanes_flat)
);
// ── Random number generator ──
random128 u_random_128 (
.clk (clk),
.rst_n (rst_n),
.enable(random_enable),
.seed ({NOISE_SEED, NOISE_SEED}),
.out (random_num)
);
endmodule