feat(hw): add banked CAM pipeline with grouped read/write noise

- Add cam_core_banked.sv with 8-lane banked CAM core
- Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection
- Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG
- Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection
- Add popcount_pipeline.sv for pipelined popcount operations
- Refactor test_cam_basic.py with parametrized DUT introspection helpers
- Add Python ref_model match_top1_with_read_noise() for read noise verification
- Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups
- Add new testbenches: test_cam_core_banked, test_cam_read_noise,
  test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise
  
breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8

hw/sim/Makefile

@@ -1,22 +1,12 @@
 SIM ?= verilator
 TOPLEVEL_LANG ?= verilog
-TOPLEVEL := cam_top
+TOPLEVEL ?= cam_top
 
-# MODULE ?= tests.test_cam_basic
 COCOTB_TEST_MODULES ?= tests.test_cam_basic
 
-NUM_ROWS ?= 512
+NUM_ROWS ?= 4096
 HASH_BITS ?= 512
-LANES ?= 16
-
-# Noise parameters
-NOISE_EN          ?= 1
-NOISE_RATE_NUM    ?= 1
-NOISE_RATE_DEN    ?= 100
-NOISE_BITS        ?= 8
-# NOISE_SEED cannot be overridden via Makefile due to Verilator -G quoting issues
-# with 64'h hex literals. To change the seed, edit the default in cam_top.sv
-# (sim top is cam_top, which passes it to cam_noisy).
+LANES ?= 8
 
 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
 
@@ -25,11 +15,42 @@ COMPILE_ARGS += -I$(PWD)/../rtl
 COMPILE_ARGS += +define+SIM_DEBUG
 COMPILE_ARGS += $(EXTRA_DEFINES)
 
-# Noise parameter overrides via Verilator -G
-COMPILE_ARGS += -GNOISE_EN=$(NOISE_EN)
-COMPILE_ARGS += -GNOISE_RATE_NUM=$(NOISE_RATE_NUM)
-COMPILE_ARGS += -GNOISE_RATE_DEN=$(NOISE_RATE_DEN)
-COMPILE_ARGS += -GNOISE_BITS=$(NOISE_BITS)
+# Noise parameters — only passed when explicitly set (non-empty).
+# For cam_noisy/cam_top tests, pass WRITE_NOISE_*=... READ_NOISE_*=...
+# For individual module tests, leave them unset to skip.
+WRITE_NOISE_EN          ?= $(NOISE_EN)
+WRITE_NOISE_RATE_NUM    ?= $(NOISE_RATE_NUM)
+WRITE_NOISE_RATE_DEN    ?= $(NOISE_RATE_DEN)
+WRITE_NOISE_BITS        ?= $(NOISE_BITS)
+READ_NOISE_EN           ?=
+READ_NOISE_RATE_NUM     ?=
+READ_NOISE_RATE_DEN     ?=
+READ_NOISE_BITS         ?=
+
+ifneq ($(strip $(WRITE_NOISE_EN)),)
+COMPILE_ARGS += -GWRITE_NOISE_EN=$(WRITE_NOISE_EN)
+endif
+ifneq ($(strip $(WRITE_NOISE_RATE_NUM)),)
+COMPILE_ARGS += -GWRITE_NOISE_RATE_NUM=$(WRITE_NOISE_RATE_NUM)
+endif
+ifneq ($(strip $(WRITE_NOISE_RATE_DEN)),)
+COMPILE_ARGS += -GWRITE_NOISE_RATE_DEN=$(WRITE_NOISE_RATE_DEN)
+endif
+ifneq ($(strip $(WRITE_NOISE_BITS)),)
+COMPILE_ARGS += -GWRITE_NOISE_BITS=$(WRITE_NOISE_BITS)
+endif
+ifneq ($(strip $(READ_NOISE_EN)),)
+COMPILE_ARGS += -GREAD_NOISE_EN=$(READ_NOISE_EN)
+endif
+ifneq ($(strip $(READ_NOISE_RATE_NUM)),)
+COMPILE_ARGS += -GREAD_NOISE_RATE_NUM=$(READ_NOISE_RATE_NUM)
+endif
+ifneq ($(strip $(READ_NOISE_RATE_DEN)),)
+COMPILE_ARGS += -GREAD_NOISE_RATE_DEN=$(READ_NOISE_RATE_DEN)
+endif
+ifneq ($(strip $(READ_NOISE_BITS)),)
+COMPILE_ARGS += -GREAD_NOISE_BITS=$(READ_NOISE_BITS)
+endif
 
 # Cleaner terminal output
 export QUIET ?= 1
@@ -48,6 +69,12 @@ VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
 VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
 VERILOG_SOURCES += $(PWD)/../rtl/random/random128.sv
+VERILOG_SOURCES += $(PWD)/../rtl/noise_mask_grouped.sv
+VERILOG_SOURCES += $(PWD)/../rtl/cam_core_banked.sv
+VERILOG_SOURCES += $(PWD)/../rtl/cam_write_noise.sv
+VERILOG_SOURCES += $(PWD)/../rtl/cam_read_noise.sv
+VERILOG_SOURCES += $(PWD)/../rtl/popcount_pipeline.sv
+VERILOG_SOURCES += $(PWD)/../rtl/match_engine_pipeline.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv
 VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv