feat(hw): add banked CAM pipeline with grouped read/write noise

- Add cam_core_banked.sv with 8-lane banked CAM core
- Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection
- Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG
- Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection
- Add popcount_pipeline.sv for pipelined popcount operations
- Refactor test_cam_basic.py with parametrized DUT introspection helpers
- Add Python ref_model match_top1_with_read_noise() for read noise verification
- Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups
- Add new testbenches: test_cam_core_banked, test_cam_read_noise,
  test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise
  
breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8

hw/rtl/cam_params.svh

@@ -21,7 +21,7 @@
 
 // Number of CAM rows.
 `ifndef NUM_ROWS
-`define NUM_ROWS 512
+`define NUM_ROWS 4096
 `endif
 
 // Width of the hash value stored per row.
@@ -31,7 +31,7 @@
 
 // Number of parallel comparison lanes.
 `ifndef LANES
-`define LANES 16
+`define LANES 8
 `endif
 
 // Bits required to represent a row index.
@@ -48,7 +48,7 @@
 // Used as the initial best-index value before any match is found.
 localparam logic [(`ROW_BITS)-1:0] TIE_BREAK_SENTINEL = {(`ROW_BITS){1'b1}};
 
-// Current fixed parameters require NUM_ROWS divisible by LANES.
-// Non-divisible tail-group valid-mask is not implemented in this round.
+// First banked-pipeline implementation requires NUM_ROWS divisible by LANES.
+// Tail lanes and unaligned read batches are intentionally out of scope.
 
 `endif // CAM_PARAMS_SVH