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https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
feat(hw): add banked CAM pipeline with grouped read/write noise
- Add cam_core_banked.sv with 8-lane banked CAM core - Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection - Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG - Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection - Add popcount_pipeline.sv for pipelined popcount operations - Refactor test_cam_basic.py with parametrized DUT introspection helpers - Add Python ref_model match_top1_with_read_noise() for read noise verification - Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups - Add new testbenches: test_cam_core_banked, test_cam_read_noise, test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8
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@@ -1,189 +1,95 @@
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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// Design constraints:
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// HASH_BITS % NOISE_BITS == 0
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// GROUP_BITS (= HASH_BITS / NOISE_BITS) == 64 (needed for 6-bit index)
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// NOISE_BITS * GROUP_RAND_BITS <= 128
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// 0 <= NOISE_RATE_NUM <= NOISE_RATE_DEN
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// NOISE_RATE_DEN > 0
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// NOISE_SEED != 64'd0
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// NOISE_BITS > 0
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module cam_noisy #(
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parameter bit NOISE_EN = 1'b1,
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parameter int NOISE_RATE_NUM = 70,
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parameter int NOISE_RATE_DEN = 100,
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parameter logic [63:0] NOISE_SEED = 64'hB504_F32D_B504_F32D,
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parameter int NOISE_BITS = 8
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter int WRITE_NOISE_BITS = 8,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D,
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parameter bit READ_NOISE_EN = 1'b1,
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parameter int READ_NOISE_RATE_NUM = 1,
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parameter int READ_NOISE_RATE_DEN = 100,
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parameter int READ_NOISE_BITS = 8,
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parameter logic [63:0] READ_NOISE_SEED = 64'h6A09_E667_F3BC_C909
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) (
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input logic clk,
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input logic rst_n,
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// Write interface (handshake)
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input logic wr_valid,
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output logic wr_ready,
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input logic [ (`ROW_BITS)-1:0] wr_addr,
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input logic [(`HASH_BITS)-1:0] write_hash,
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// Read interface (passthrough to cam_core, combinational read)
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input logic [ (`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_addr,
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input logic [(`HASH_BITS)-1:0] write_hash,
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input logic rd_valid_i,
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input logic [(`ROW_BITS)-1:0] rd_base_row_i,
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output logic rd_valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] rd_row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hashes_o,
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output logic [(`LANES)-1:0] rd_lane_valid_o
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);
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// ── Local parameters ──
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localparam int GROUP_BITS = `HASH_BITS / NOISE_BITS;
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localparam int BIT_INDEX_BITS = 6;
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localparam int SAMPLE_BITS = 8;
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localparam int GROUP_RAND_BITS = BIT_INDEX_BITS + SAMPLE_BITS; // 14
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localparam int SAMPLE_RANGE = 2 ** SAMPLE_BITS; // 256
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localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
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// ── Elaboration-time parameter checks ──
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initial begin
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if (NOISE_BITS <= 0)
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$fatal(1, "NOISE_BITS must be > 0, got %0d", NOISE_BITS);
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if (`HASH_BITS % NOISE_BITS != 0)
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$fatal(1, "HASH_BITS (%0d) must be divisible by NOISE_BITS (%0d)", `HASH_BITS, NOISE_BITS);
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if (GROUP_BITS != 64)
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$fatal(1, "GROUP_BITS (= HASH_BITS/NOISE_BITS) must equal 64 for 6-bit index, got %0d", GROUP_BITS);
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if (NOISE_BITS * GROUP_RAND_BITS > 128)
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$fatal(1, "NOISE_BITS*GROUP_RAND_BITS must be <= 128, got %0d", NOISE_BITS * GROUP_RAND_BITS);
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if (NOISE_RATE_DEN <= 0)
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$fatal(1, "NOISE_RATE_DEN must be > 0, got %0d", NOISE_RATE_DEN);
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if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN)
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$fatal(1, "NOISE_RATE_NUM (%0d) must be in [0, NOISE_RATE_DEN=%0d]", NOISE_RATE_NUM, NOISE_RATE_DEN);
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if (NOISE_SEED == 64'd0)
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$fatal(1, "NOISE_SEED must be nonzero — xorshift128/random128 with zero seed never advances");
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end
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// ── FSM states ──
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typedef enum logic [1:0] {
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S_IDLE,
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S_GEN_MASK,
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S_COMMIT
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} state_t;
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state_t curr_state, next_state;
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// ── Latch registers ──
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logic [(`ROW_BITS)-1:0] addr_q;
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logic [(`HASH_BITS)-1:0] write_hash_q;
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// ── Noise generation ──
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logic [(`HASH_BITS)-1:0] flip_mask;
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logic [127:0] random_num;
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// ── Combinational next-mask helper ──
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// Computes flip_mask_next from fresh random_num in one cycle.
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logic [(`HASH_BITS)-1:0] flip_mask_next;
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always_comb begin
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flip_mask_next = '0;
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for (int i = 0; i < NOISE_BITS; i++) begin
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if (random_num[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
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flip_mask_next[i * GROUP_BITS + random_num[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
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end
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end
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end
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// ── Noisy hash for cam_core write ──
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logic [(`HASH_BITS)-1:0] noisy_hash;
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assign noisy_hash = write_hash_q ^ flip_mask;
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// ── wr_ready: only in IDLE ──
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assign wr_ready = (curr_state == S_IDLE);
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// ── random128 enable: advance random on accepted noisy write ──
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logic random_enable;
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assign random_enable = wr_ready && wr_valid && NOISE_EN && (NOISE_RATE_NUM > 0);
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// ── FSM block 1: state register ──
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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curr_state <= S_IDLE;
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end else begin
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curr_state <= next_state;
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end
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end
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// ── FSM block 2: next-state logic ──
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always_comb begin
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next_state = curr_state;
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case (curr_state)
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S_IDLE: begin
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if (wr_valid && wr_ready) begin
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if (NOISE_EN && (NOISE_RATE_NUM > 0)) next_state = S_GEN_MASK;
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else next_state = S_COMMIT;
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end
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end
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S_GEN_MASK: begin
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next_state = S_COMMIT;
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end
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S_COMMIT: begin
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next_state = S_IDLE;
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end
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default: next_state = S_IDLE;
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endcase
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end
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// ── FSM block 3: state actions / datapath registers ──
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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addr_q <= '0;
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write_hash_q <= '0;
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flip_mask <= '0;
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end else begin
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case (curr_state)
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S_IDLE: begin
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flip_mask <= '0;
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if (wr_valid && wr_ready) begin
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addr_q <= wr_addr;
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write_hash_q <= write_hash;
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end
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end
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S_GEN_MASK: begin
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flip_mask <= flip_mask_next;
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end
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S_COMMIT: begin
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// Write happens via combinational core_wr_en
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end
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default: ; // No-op
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endcase
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end
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end
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// ── cam_core instance ──
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logic core_wr_en;
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logic [ (`ROW_BITS)-1:0] core_wr_row;
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// ── Intermediate wires between pipeline stages ──
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logic core_wr_valid;
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logic [(`ROW_BITS)-1:0] core_wr_row;
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logic [(`HASH_BITS)-1:0] core_wr_hash;
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assign core_wr_en = (curr_state == S_COMMIT);
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assign core_wr_row = addr_q;
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assign core_wr_hash = noisy_hash;
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logic core_rd_valid;
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logic [(`LANES)*(`ROW_BITS)-1:0] core_rd_row_ids;
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logic [(`LANES)*(`HASH_BITS)-1:0] core_rd_hashes;
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logic [(`LANES)-1:0] core_rd_lane_valid;
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cam_core u_core (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (core_wr_en),
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.wr_row (core_wr_row),
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.wr_hash (core_wr_hash),
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.rd_addr_lanes_flat(rd_addr_lanes_flat),
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.rd_hash_lanes_flat(rd_hash_lanes_flat)
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// ── Write noise pipeline ──
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cam_write_noise #(
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.WRITE_NOISE_EN (WRITE_NOISE_EN),
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.WRITE_NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
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.WRITE_NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN),
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.WRITE_NOISE_BITS (WRITE_NOISE_BITS),
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.WRITE_NOISE_SEED (WRITE_NOISE_SEED)
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) u_write_noise (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (wr_valid),
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.wr_ready (wr_ready),
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.wr_row (wr_addr),
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.wr_hash (write_hash),
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.core_wr_valid (core_wr_valid),
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.core_wr_row (core_wr_row),
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.core_wr_hash (core_wr_hash)
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);
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// ── Random number generator ──
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random128 u_random_128 (
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.clk (clk),
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.rst_n (rst_n),
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.enable(random_enable),
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.seed ({NOISE_SEED, NOISE_SEED}),
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.out (random_num)
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// ── Banked synchronous BRAM storage ──
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cam_core_banked u_core_banked (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (core_wr_valid),
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.wr_ready (),
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.wr_row (core_wr_row),
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.wr_hash (core_wr_hash),
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.rd_valid_i (rd_valid_i),
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.rd_base_row_i (rd_base_row_i),
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.rd_valid_o (core_rd_valid),
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.rd_row_ids_o (core_rd_row_ids),
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.rd_hashes_o (core_rd_hashes),
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.rd_lane_valid_o (core_rd_lane_valid)
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);
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// ── Read noise pipeline ──
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cam_read_noise #(
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.READ_NOISE_EN (READ_NOISE_EN),
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.READ_NOISE_RATE_NUM (READ_NOISE_RATE_NUM),
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.READ_NOISE_RATE_DEN (READ_NOISE_RATE_DEN),
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.READ_NOISE_BITS (READ_NOISE_BITS),
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.READ_NOISE_SEED (READ_NOISE_SEED)
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) u_read_noise (
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.clk (clk),
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.rst_n (rst_n),
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.valid_i (core_rd_valid),
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.row_ids_i (core_rd_row_ids),
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.hashes_i (core_rd_hashes),
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.lane_valid_i (core_rd_lane_valid),
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.valid_o (rd_valid_o),
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.row_ids_o (rd_row_ids_o),
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.hashes_noisy_o (rd_hashes_o),
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.lane_valid_o (rd_lane_valid_o)
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);
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endmodule
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