mirror of
https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
feat(hw): add banked CAM pipeline with grouped read/write noise
- Add cam_core_banked.sv with 8-lane banked CAM core - Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection - Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG - Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection - Add popcount_pipeline.sv for pipelined popcount operations - Refactor test_cam_basic.py with parametrized DUT introspection helpers - Add Python ref_model match_top1_with_read_noise() for read noise verification - Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups - Add new testbenches: test_cam_core_banked, test_cam_read_noise, test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8
This commit is contained in:
57
hw/rtl/cam_core_banked.sv
Normal file
57
hw/rtl/cam_core_banked.sv
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@@ -0,0 +1,57 @@
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_core_banked (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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input logic rd_valid_i,
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input logic [(`ROW_BITS)-1:0] rd_base_row_i,
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output logic rd_valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] rd_row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hashes_o,
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output logic [(`LANES)-1:0] rd_lane_valid_o
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);
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localparam int BANKS = `LANES;
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localparam int BANK_DEPTH = `NUM_ROWS / `LANES;
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(* ram_style = "block" *) logic [(`HASH_BITS)-1:0] bank_mem [0:BANKS-1][0:BANK_DEPTH-1];
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assign wr_ready = 1'b1;
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initial begin
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if (`NUM_ROWS % `LANES != 0) $fatal(1, "NUM_ROWS must be divisible by LANES");
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end
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always_ff @(posedge clk) begin
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if (wr_valid) begin
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bank_mem[wr_row % `LANES][wr_row / `LANES] <= wr_hash;
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end
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_valid_o <= 1'b0;
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rd_row_ids_o <= '0;
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rd_hashes_o <= '0;
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rd_lane_valid_o <= '0;
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end else begin
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rd_valid_o <= rd_valid_i;
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rd_lane_valid_o <= rd_valid_i ? {`LANES{1'b1}} : '0;
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if (rd_valid_i && ((rd_base_row_i % `LANES) != 0)) begin
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$fatal(1, "rd_base_row_i must be LANES-aligned");
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end
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for (int lane = 0; lane < `LANES; lane++) begin
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rd_row_ids_o[lane*`ROW_BITS +: `ROW_BITS] <= rd_base_row_i + lane[(`ROW_BITS)-1:0];
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rd_hashes_o[lane*`HASH_BITS +: `HASH_BITS] <= bank_mem[lane][rd_base_row_i / `LANES];
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end
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end
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end
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endmodule
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@@ -1,189 +1,95 @@
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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// Design constraints:
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// HASH_BITS % NOISE_BITS == 0
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// GROUP_BITS (= HASH_BITS / NOISE_BITS) == 64 (needed for 6-bit index)
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// NOISE_BITS * GROUP_RAND_BITS <= 128
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// 0 <= NOISE_RATE_NUM <= NOISE_RATE_DEN
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// NOISE_RATE_DEN > 0
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// NOISE_SEED != 64'd0
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// NOISE_BITS > 0
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module cam_noisy #(
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parameter bit NOISE_EN = 1'b1,
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parameter int NOISE_RATE_NUM = 70,
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parameter int NOISE_RATE_DEN = 100,
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parameter logic [63:0] NOISE_SEED = 64'hB504_F32D_B504_F32D,
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parameter int NOISE_BITS = 8
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter int WRITE_NOISE_BITS = 8,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D,
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parameter bit READ_NOISE_EN = 1'b1,
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parameter int READ_NOISE_RATE_NUM = 1,
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parameter int READ_NOISE_RATE_DEN = 100,
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parameter int READ_NOISE_BITS = 8,
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parameter logic [63:0] READ_NOISE_SEED = 64'h6A09_E667_F3BC_C909
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) (
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input logic clk,
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input logic rst_n,
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// Write interface (handshake)
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input logic wr_valid,
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output logic wr_ready,
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input logic [ (`ROW_BITS)-1:0] wr_addr,
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input logic [(`HASH_BITS)-1:0] write_hash,
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// Read interface (passthrough to cam_core, combinational read)
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input logic [ (`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_addr,
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input logic [(`HASH_BITS)-1:0] write_hash,
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input logic rd_valid_i,
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input logic [(`ROW_BITS)-1:0] rd_base_row_i,
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output logic rd_valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] rd_row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hashes_o,
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output logic [(`LANES)-1:0] rd_lane_valid_o
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);
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// ── Local parameters ──
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localparam int GROUP_BITS = `HASH_BITS / NOISE_BITS;
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localparam int BIT_INDEX_BITS = 6;
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localparam int SAMPLE_BITS = 8;
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localparam int GROUP_RAND_BITS = BIT_INDEX_BITS + SAMPLE_BITS; // 14
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localparam int SAMPLE_RANGE = 2 ** SAMPLE_BITS; // 256
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localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
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// ── Elaboration-time parameter checks ──
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initial begin
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if (NOISE_BITS <= 0)
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$fatal(1, "NOISE_BITS must be > 0, got %0d", NOISE_BITS);
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if (`HASH_BITS % NOISE_BITS != 0)
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$fatal(1, "HASH_BITS (%0d) must be divisible by NOISE_BITS (%0d)", `HASH_BITS, NOISE_BITS);
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if (GROUP_BITS != 64)
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$fatal(1, "GROUP_BITS (= HASH_BITS/NOISE_BITS) must equal 64 for 6-bit index, got %0d", GROUP_BITS);
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if (NOISE_BITS * GROUP_RAND_BITS > 128)
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$fatal(1, "NOISE_BITS*GROUP_RAND_BITS must be <= 128, got %0d", NOISE_BITS * GROUP_RAND_BITS);
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if (NOISE_RATE_DEN <= 0)
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$fatal(1, "NOISE_RATE_DEN must be > 0, got %0d", NOISE_RATE_DEN);
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if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN)
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$fatal(1, "NOISE_RATE_NUM (%0d) must be in [0, NOISE_RATE_DEN=%0d]", NOISE_RATE_NUM, NOISE_RATE_DEN);
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if (NOISE_SEED == 64'd0)
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$fatal(1, "NOISE_SEED must be nonzero — xorshift128/random128 with zero seed never advances");
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end
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// ── FSM states ──
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typedef enum logic [1:0] {
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S_IDLE,
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S_GEN_MASK,
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S_COMMIT
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} state_t;
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state_t curr_state, next_state;
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// ── Latch registers ──
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logic [(`ROW_BITS)-1:0] addr_q;
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logic [(`HASH_BITS)-1:0] write_hash_q;
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// ── Noise generation ──
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logic [(`HASH_BITS)-1:0] flip_mask;
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logic [127:0] random_num;
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// ── Combinational next-mask helper ──
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// Computes flip_mask_next from fresh random_num in one cycle.
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logic [(`HASH_BITS)-1:0] flip_mask_next;
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always_comb begin
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flip_mask_next = '0;
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for (int i = 0; i < NOISE_BITS; i++) begin
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if (random_num[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
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flip_mask_next[i * GROUP_BITS + random_num[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
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end
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end
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end
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// ── Noisy hash for cam_core write ──
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logic [(`HASH_BITS)-1:0] noisy_hash;
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assign noisy_hash = write_hash_q ^ flip_mask;
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// ── wr_ready: only in IDLE ──
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assign wr_ready = (curr_state == S_IDLE);
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// ── random128 enable: advance random on accepted noisy write ──
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logic random_enable;
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assign random_enable = wr_ready && wr_valid && NOISE_EN && (NOISE_RATE_NUM > 0);
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// ── FSM block 1: state register ──
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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curr_state <= S_IDLE;
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end else begin
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curr_state <= next_state;
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end
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end
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// ── FSM block 2: next-state logic ──
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always_comb begin
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next_state = curr_state;
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case (curr_state)
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S_IDLE: begin
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if (wr_valid && wr_ready) begin
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if (NOISE_EN && (NOISE_RATE_NUM > 0)) next_state = S_GEN_MASK;
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else next_state = S_COMMIT;
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end
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end
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S_GEN_MASK: begin
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next_state = S_COMMIT;
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end
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S_COMMIT: begin
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next_state = S_IDLE;
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end
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default: next_state = S_IDLE;
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endcase
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end
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// ── FSM block 3: state actions / datapath registers ──
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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addr_q <= '0;
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write_hash_q <= '0;
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flip_mask <= '0;
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end else begin
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case (curr_state)
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S_IDLE: begin
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flip_mask <= '0;
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if (wr_valid && wr_ready) begin
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addr_q <= wr_addr;
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write_hash_q <= write_hash;
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end
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end
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S_GEN_MASK: begin
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flip_mask <= flip_mask_next;
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end
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S_COMMIT: begin
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// Write happens via combinational core_wr_en
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end
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default: ; // No-op
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endcase
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end
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end
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// ── cam_core instance ──
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logic core_wr_en;
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logic [ (`ROW_BITS)-1:0] core_wr_row;
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// ── Intermediate wires between pipeline stages ──
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logic core_wr_valid;
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logic [(`ROW_BITS)-1:0] core_wr_row;
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logic [(`HASH_BITS)-1:0] core_wr_hash;
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assign core_wr_en = (curr_state == S_COMMIT);
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assign core_wr_row = addr_q;
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assign core_wr_hash = noisy_hash;
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logic core_rd_valid;
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logic [(`LANES)*(`ROW_BITS)-1:0] core_rd_row_ids;
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logic [(`LANES)*(`HASH_BITS)-1:0] core_rd_hashes;
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logic [(`LANES)-1:0] core_rd_lane_valid;
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cam_core u_core (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (core_wr_en),
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.wr_row (core_wr_row),
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.wr_hash (core_wr_hash),
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.rd_addr_lanes_flat(rd_addr_lanes_flat),
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.rd_hash_lanes_flat(rd_hash_lanes_flat)
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// ── Write noise pipeline ──
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cam_write_noise #(
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.WRITE_NOISE_EN (WRITE_NOISE_EN),
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.WRITE_NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
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.WRITE_NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN),
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.WRITE_NOISE_BITS (WRITE_NOISE_BITS),
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.WRITE_NOISE_SEED (WRITE_NOISE_SEED)
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) u_write_noise (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (wr_valid),
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.wr_ready (wr_ready),
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.wr_row (wr_addr),
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.wr_hash (write_hash),
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.core_wr_valid (core_wr_valid),
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.core_wr_row (core_wr_row),
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.core_wr_hash (core_wr_hash)
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);
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// ── Random number generator ──
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random128 u_random_128 (
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.clk (clk),
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.rst_n (rst_n),
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.enable(random_enable),
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.seed ({NOISE_SEED, NOISE_SEED}),
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.out (random_num)
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// ── Banked synchronous BRAM storage ──
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cam_core_banked u_core_banked (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (core_wr_valid),
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.wr_ready (),
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.wr_row (core_wr_row),
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.wr_hash (core_wr_hash),
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.rd_valid_i (rd_valid_i),
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.rd_base_row_i (rd_base_row_i),
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.rd_valid_o (core_rd_valid),
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.rd_row_ids_o (core_rd_row_ids),
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.rd_hashes_o (core_rd_hashes),
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.rd_lane_valid_o (core_rd_lane_valid)
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);
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// ── Read noise pipeline ──
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cam_read_noise #(
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.READ_NOISE_EN (READ_NOISE_EN),
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.READ_NOISE_RATE_NUM (READ_NOISE_RATE_NUM),
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.READ_NOISE_RATE_DEN (READ_NOISE_RATE_DEN),
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.READ_NOISE_BITS (READ_NOISE_BITS),
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.READ_NOISE_SEED (READ_NOISE_SEED)
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) u_read_noise (
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.clk (clk),
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.rst_n (rst_n),
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.valid_i (core_rd_valid),
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.row_ids_i (core_rd_row_ids),
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.hashes_i (core_rd_hashes),
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.lane_valid_i (core_rd_lane_valid),
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.valid_o (rd_valid_o),
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.row_ids_o (rd_row_ids_o),
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.hashes_noisy_o (rd_hashes_o),
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.lane_valid_o (rd_lane_valid_o)
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);
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endmodule
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@@ -21,7 +21,7 @@
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// Number of CAM rows.
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`ifndef NUM_ROWS
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`define NUM_ROWS 512
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`define NUM_ROWS 4096
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`endif
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// Width of the hash value stored per row.
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@@ -31,7 +31,7 @@
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// Number of parallel comparison lanes.
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`ifndef LANES
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`define LANES 16
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`define LANES 8
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`endif
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// Bits required to represent a row index.
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@@ -48,7 +48,7 @@
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// Used as the initial best-index value before any match is found.
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localparam logic [(`ROW_BITS)-1:0] TIE_BREAK_SENTINEL = {(`ROW_BITS){1'b1}};
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// Current fixed parameters require NUM_ROWS divisible by LANES.
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// Non-divisible tail-group valid-mask is not implemented in this round.
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// First banked-pipeline implementation requires NUM_ROWS divisible by LANES.
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// Tail lanes and unaligned read batches are intentionally out of scope.
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`endif // CAM_PARAMS_SVH
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85
hw/rtl/cam_read_noise.sv
Normal file
85
hw/rtl/cam_read_noise.sv
Normal file
@@ -0,0 +1,85 @@
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_read_noise #(
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parameter bit READ_NOISE_EN = 1'b1,
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parameter int READ_NOISE_RATE_NUM = 1,
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parameter int READ_NOISE_RATE_DEN = 100,
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parameter int READ_NOISE_BITS = 8,
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parameter logic [63:0] READ_NOISE_SEED = 64'h6A09_E667_F3BC_C909
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) (
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input logic clk,
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input logic rst_n,
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input logic valid_i,
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input logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_i,
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input logic [(`LANES)*(`HASH_BITS)-1:0] hashes_i,
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input logic [(`LANES)-1:0] lane_valid_i,
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output logic valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] hashes_noisy_o,
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output logic [(`LANES)-1:0] lane_valid_o
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);
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logic valid_q;
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logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_q;
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logic [(`LANES)*(`HASH_BITS)-1:0] hashes_q;
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logic [(`LANES)-1:0] lane_valid_q;
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logic [127:0] random_num [0:`LANES-1];
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logic [(`HASH_BITS)-1:0] mask [0:`LANES-1];
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initial begin
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if (READ_NOISE_SEED == 64'd0) $fatal(1, "READ_NOISE_SEED must be nonzero");
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end
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generate
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for (genvar lane = 0; lane < `LANES; lane++) begin : gen_lane_noise
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localparam logic [63:0] LANE_SALT = 64'(lane + 1) * 64'h9E37_79B9_7F4A_7C15;
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random128 u_random_read (
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.clk (clk),
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.rst_n (rst_n),
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.enable(valid_i && lane_valid_i[lane] && READ_NOISE_EN && (READ_NOISE_RATE_NUM > 0)),
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.seed ({(READ_NOISE_SEED ^ LANE_SALT), (READ_NOISE_SEED ^ LANE_SALT)}),
|
||||
.out (random_num[lane])
|
||||
);
|
||||
|
||||
noise_mask_grouped #(
|
||||
.HASH_BITS (`HASH_BITS),
|
||||
.NOISE_BITS (READ_NOISE_BITS),
|
||||
.NOISE_RATE_NUM (READ_NOISE_RATE_NUM),
|
||||
.NOISE_RATE_DEN (READ_NOISE_RATE_DEN)
|
||||
) u_mask (
|
||||
.random_i(random_num[lane]),
|
||||
.mask_o (mask[lane])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
valid_q <= 1'b0;
|
||||
row_ids_q <= '0;
|
||||
hashes_q <= '0;
|
||||
lane_valid_q <= '0;
|
||||
valid_o <= 1'b0;
|
||||
row_ids_o <= '0;
|
||||
hashes_noisy_o <= '0;
|
||||
lane_valid_o <= '0;
|
||||
end else begin
|
||||
valid_q <= valid_i;
|
||||
row_ids_q <= row_ids_i;
|
||||
hashes_q <= hashes_i;
|
||||
lane_valid_q <= lane_valid_i;
|
||||
|
||||
valid_o <= valid_q;
|
||||
row_ids_o <= row_ids_q;
|
||||
lane_valid_o <= lane_valid_q;
|
||||
for (int lane = 0; lane < `LANES; lane++) begin
|
||||
if (READ_NOISE_EN && (READ_NOISE_RATE_NUM > 0) && lane_valid_q[lane]) begin
|
||||
hashes_noisy_o[lane*`HASH_BITS +: `HASH_BITS] <= hashes_q[lane*`HASH_BITS +: `HASH_BITS] ^ mask[lane];
|
||||
end else begin
|
||||
hashes_noisy_o[lane*`HASH_BITS +: `HASH_BITS] <= hashes_q[lane*`HASH_BITS +: `HASH_BITS];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -2,11 +2,16 @@
|
||||
`include "cam_params.svh"
|
||||
|
||||
module cam_top #(
|
||||
parameter bit NOISE_EN = 1'b1,
|
||||
parameter int NOISE_RATE_NUM = 1,
|
||||
parameter int NOISE_RATE_DEN = 100,
|
||||
parameter int NOISE_BITS = 8,
|
||||
parameter logic [63:0] NOISE_SEED = 64'hB504_F32D_B504_F32D
|
||||
parameter bit WRITE_NOISE_EN = 1'b1,
|
||||
parameter int WRITE_NOISE_RATE_NUM = 1,
|
||||
parameter int WRITE_NOISE_RATE_DEN = 100,
|
||||
parameter int WRITE_NOISE_BITS = 8,
|
||||
parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D,
|
||||
parameter bit READ_NOISE_EN = 1'b0,
|
||||
parameter int READ_NOISE_RATE_NUM = 1,
|
||||
parameter int READ_NOISE_RATE_DEN = 100,
|
||||
parameter int READ_NOISE_BITS = 8,
|
||||
parameter logic [63:0] READ_NOISE_SEED = 64'h6A09_E667_F3BC_C909
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
@@ -36,7 +41,7 @@ module cam_top #(
|
||||
);
|
||||
|
||||
// ── Internal signals ──
|
||||
logic storage_wr_ready; // cam_noisy idle
|
||||
logic storage_wr_ready; // cam_noisy write-side ready
|
||||
logic match_query_ready; // match_engine idle
|
||||
logic match_busy; // match_engine scanning/result pending
|
||||
|
||||
@@ -45,8 +50,8 @@ module cam_top #(
|
||||
logic match_query_valid;
|
||||
|
||||
// ── Half-duplex arbitration (write-priority) ──
|
||||
// When both wr_valid and query_valid are high, write wins.
|
||||
assign wr_ready = storage_wr_ready && match_query_ready;
|
||||
// Active query scan blocks new writes.
|
||||
assign wr_ready = storage_wr_ready && match_query_ready && !match_busy;
|
||||
assign query_ready = storage_wr_ready && match_query_ready && !wr_valid;
|
||||
assign busy = (!storage_wr_ready) || match_busy || (!match_query_ready);
|
||||
|
||||
@@ -54,42 +59,59 @@ module cam_top #(
|
||||
assign storage_wr_valid = wr_valid && wr_ready;
|
||||
assign match_query_valid = query_valid && query_ready;
|
||||
|
||||
// ── Shared read bus ──
|
||||
wire [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat;
|
||||
wire [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat;
|
||||
// ── Read request/response bus between cam_noisy and match_engine_pipeline ──
|
||||
wire rd_req_valid;
|
||||
wire [(`ROW_BITS)-1:0] rd_req_base_row;
|
||||
wire rd_resp_valid;
|
||||
wire [(`LANES)*(`ROW_BITS)-1:0] rd_resp_row_ids;
|
||||
wire [(`LANES)*(`HASH_BITS)-1:0] rd_resp_hashes;
|
||||
wire [(`LANES)-1:0] rd_resp_lane_valid;
|
||||
|
||||
cam_noisy #(
|
||||
.NOISE_EN (NOISE_EN),
|
||||
.NOISE_RATE_NUM (NOISE_RATE_NUM),
|
||||
.NOISE_RATE_DEN (NOISE_RATE_DEN),
|
||||
.NOISE_BITS (NOISE_BITS),
|
||||
.NOISE_SEED (NOISE_SEED)
|
||||
.WRITE_NOISE_EN (WRITE_NOISE_EN),
|
||||
.WRITE_NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
|
||||
.WRITE_NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN),
|
||||
.WRITE_NOISE_BITS (WRITE_NOISE_BITS),
|
||||
.WRITE_NOISE_SEED (WRITE_NOISE_SEED),
|
||||
.READ_NOISE_EN (READ_NOISE_EN),
|
||||
.READ_NOISE_RATE_NUM (READ_NOISE_RATE_NUM),
|
||||
.READ_NOISE_RATE_DEN (READ_NOISE_RATE_DEN),
|
||||
.READ_NOISE_BITS (READ_NOISE_BITS),
|
||||
.READ_NOISE_SEED (READ_NOISE_SEED)
|
||||
) u_noisy (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.wr_valid (storage_wr_valid),
|
||||
.wr_ready (storage_wr_ready),
|
||||
.wr_addr (wr_addr),
|
||||
.write_hash (write_hash),
|
||||
.rd_addr_lanes_flat (rd_addr_lanes_flat),
|
||||
.rd_hash_lanes_flat (rd_hash_lanes_flat)
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.wr_valid (storage_wr_valid),
|
||||
.wr_ready (storage_wr_ready),
|
||||
.wr_addr (wr_addr),
|
||||
.write_hash (write_hash),
|
||||
.rd_valid_i (rd_req_valid),
|
||||
.rd_base_row_i (rd_req_base_row),
|
||||
.rd_valid_o (rd_resp_valid),
|
||||
.rd_row_ids_o (rd_resp_row_ids),
|
||||
.rd_hashes_o (rd_resp_hashes),
|
||||
.rd_lane_valid_o (rd_resp_lane_valid)
|
||||
);
|
||||
|
||||
match_engine u_match (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.query_valid (match_query_valid),
|
||||
.query_ready (match_query_ready),
|
||||
.query_hash (query_hash),
|
||||
.result_valid (result_valid),
|
||||
.result_ready (result_ready),
|
||||
.result_row (top1_index),
|
||||
.result_score (top1_score),
|
||||
.busy (match_busy),
|
||||
.rd_addr_lanes_flat (rd_addr_lanes_flat),
|
||||
.rd_hash_lanes_flat (rd_hash_lanes_flat)
|
||||
match_engine_pipeline u_match (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.query_valid (match_query_valid),
|
||||
.query_ready (match_query_ready),
|
||||
.query_hash (query_hash),
|
||||
.result_valid (result_valid),
|
||||
.result_ready (result_ready),
|
||||
.result_row (top1_index),
|
||||
.result_score (top1_score),
|
||||
.busy (match_busy),
|
||||
.rd_valid_o (rd_req_valid),
|
||||
.rd_base_row_o (rd_req_base_row),
|
||||
.rd_valid_i (rd_resp_valid),
|
||||
.rd_row_ids_i (rd_resp_row_ids),
|
||||
.rd_hashes_i (rd_resp_hashes),
|
||||
.rd_lane_valid_i (rd_resp_lane_valid)
|
||||
`ifdef SIM_DEBUG
|
||||
,.score_debug_flat (score_debug_flat)
|
||||
,.score_debug_flat (score_debug_flat)
|
||||
`endif
|
||||
);
|
||||
|
||||
|
||||
75
hw/rtl/cam_write_noise.sv
Normal file
75
hw/rtl/cam_write_noise.sv
Normal file
@@ -0,0 +1,75 @@
|
||||
`timescale 1ns / 1ps
|
||||
`include "cam_params.svh"
|
||||
|
||||
module cam_write_noise #(
|
||||
parameter bit WRITE_NOISE_EN = 1'b1,
|
||||
parameter int WRITE_NOISE_RATE_NUM = 1,
|
||||
parameter int WRITE_NOISE_RATE_DEN = 100,
|
||||
parameter int WRITE_NOISE_BITS = 8,
|
||||
parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
input logic wr_valid,
|
||||
output logic wr_ready,
|
||||
input logic [(`ROW_BITS)-1:0] wr_row,
|
||||
input logic [(`HASH_BITS)-1:0] wr_hash,
|
||||
output logic core_wr_valid,
|
||||
output logic [(`ROW_BITS)-1:0] core_wr_row,
|
||||
output logic [(`HASH_BITS)-1:0] core_wr_hash
|
||||
);
|
||||
logic pending_q;
|
||||
logic [(`ROW_BITS)-1:0] row_q;
|
||||
logic [(`HASH_BITS)-1:0] hash_q;
|
||||
logic [127:0] random_num;
|
||||
logic [(`HASH_BITS)-1:0] flip_mask;
|
||||
|
||||
assign wr_ready = !pending_q;
|
||||
|
||||
random128 u_random_write (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.enable(wr_valid && wr_ready && WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)),
|
||||
.seed ({WRITE_NOISE_SEED, WRITE_NOISE_SEED}),
|
||||
.out (random_num)
|
||||
);
|
||||
|
||||
noise_mask_grouped #(
|
||||
.HASH_BITS (`HASH_BITS),
|
||||
.NOISE_BITS (WRITE_NOISE_BITS),
|
||||
.NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
|
||||
.NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN)
|
||||
) u_mask (
|
||||
.random_i(random_num),
|
||||
.mask_o (flip_mask)
|
||||
);
|
||||
|
||||
initial begin
|
||||
if (WRITE_NOISE_SEED == 64'd0) $fatal(1, "WRITE_NOISE_SEED must be nonzero");
|
||||
end
|
||||
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
pending_q <= 1'b0;
|
||||
row_q <= '0;
|
||||
hash_q <= '0;
|
||||
core_wr_valid <= 1'b0;
|
||||
core_wr_row <= '0;
|
||||
core_wr_hash <= '0;
|
||||
end else begin
|
||||
core_wr_valid <= pending_q;
|
||||
core_wr_row <= row_q;
|
||||
if (WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)) begin
|
||||
core_wr_hash <= hash_q ^ flip_mask;
|
||||
end else begin
|
||||
core_wr_hash <= hash_q;
|
||||
end
|
||||
|
||||
pending_q <= wr_valid && wr_ready;
|
||||
if (wr_valid && wr_ready) begin
|
||||
row_q <= wr_row;
|
||||
hash_q <= wr_hash;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
140
hw/rtl/match_engine_pipeline.sv
Normal file
140
hw/rtl/match_engine_pipeline.sv
Normal file
@@ -0,0 +1,140 @@
|
||||
`timescale 1ns / 1ps
|
||||
`include "cam_params.svh"
|
||||
|
||||
module match_engine_pipeline (
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
input logic query_valid,
|
||||
output logic query_ready,
|
||||
input logic [(`HASH_BITS)-1:0] query_hash,
|
||||
output logic result_valid,
|
||||
input logic result_ready,
|
||||
output logic [(`ROW_BITS)-1:0] result_row,
|
||||
output logic [(`SCORE_BITS)-1:0] result_score,
|
||||
output logic busy,
|
||||
output logic rd_valid_o,
|
||||
output logic [(`ROW_BITS)-1:0] rd_base_row_o,
|
||||
input logic rd_valid_i,
|
||||
input logic [(`LANES)*(`ROW_BITS)-1:0] rd_row_ids_i,
|
||||
input logic [(`LANES)*(`HASH_BITS)-1:0] rd_hashes_i,
|
||||
input logic [(`LANES)-1:0] rd_lane_valid_i
|
||||
`ifdef SIM_DEBUG
|
||||
,output logic [(`NUM_ROWS)*(`SCORE_BITS)-1:0] score_debug_flat
|
||||
`endif
|
||||
);
|
||||
typedef enum logic [1:0] {S_IDLE, S_SCAN, S_DRAIN, S_DONE} state_t;
|
||||
state_t state_q;
|
||||
|
||||
logic [(`HASH_BITS)-1:0] query_q;
|
||||
logic [(`ROW_BITS)-1:0] issue_base_q;
|
||||
logic [$clog2(`NUM_ROWS/`LANES+1)-1:0] returned_q;
|
||||
logic [(`ROW_BITS)-1:0] best_row_q;
|
||||
logic [(`SCORE_BITS)-1:0] best_score_q;
|
||||
|
||||
logic [(`HASH_BITS)-1:0] match_bits [0:`LANES-1];
|
||||
logic score_valid [0:`LANES-1];
|
||||
logic [(`ROW_BITS)-1:0] score_row [0:`LANES-1];
|
||||
logic [(`SCORE_BITS)-1:0] lane_score [0:`LANES-1];
|
||||
logic [(`ROW_BITS)-1:0] batch_row;
|
||||
logic [(`SCORE_BITS)-1:0] batch_score;
|
||||
|
||||
assign query_ready = (state_q == S_IDLE);
|
||||
assign result_valid = (state_q == S_DONE);
|
||||
assign result_row = best_row_q;
|
||||
assign result_score = best_score_q;
|
||||
assign busy = (state_q != S_IDLE);
|
||||
assign rd_valid_o = (state_q == S_SCAN);
|
||||
assign rd_base_row_o = issue_base_q;
|
||||
|
||||
generate
|
||||
for (genvar lane = 0; lane < `LANES; lane++) begin : gen_scores
|
||||
assign match_bits[lane] = ~(query_q ^ rd_hashes_i[lane*`HASH_BITS +: `HASH_BITS]);
|
||||
popcount_pipeline #(
|
||||
.WIDTH(`HASH_BITS),
|
||||
.ROW_BITS(`ROW_BITS),
|
||||
.OUT_WIDTH(`SCORE_BITS)
|
||||
) u_popcount_pipeline (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n),
|
||||
.valid_i(rd_valid_i && rd_lane_valid_i[lane]),
|
||||
.row_i(rd_row_ids_i[lane*`ROW_BITS +: `ROW_BITS]),
|
||||
.bits_i(match_bits[lane]),
|
||||
.valid_o(score_valid[lane]),
|
||||
.row_o(score_row[lane]),
|
||||
.count_o(lane_score[lane])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always_comb begin
|
||||
batch_row = score_row[0];
|
||||
batch_score = lane_score[0];
|
||||
for (int lane = 1; lane < `LANES; lane++) begin
|
||||
if ((lane_score[lane] > batch_score) ||
|
||||
((lane_score[lane] == batch_score) && (score_row[lane] < batch_row))) begin
|
||||
batch_score = lane_score[lane];
|
||||
batch_row = score_row[lane];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
state_q <= S_IDLE;
|
||||
query_q <= '0;
|
||||
issue_base_q <= '0;
|
||||
returned_q <= 0;
|
||||
best_row_q <= '0;
|
||||
best_score_q <= '0;
|
||||
`ifdef SIM_DEBUG
|
||||
score_debug_flat <= '0;
|
||||
`endif
|
||||
end else begin
|
||||
unique case (state_q)
|
||||
S_IDLE: begin
|
||||
if (query_valid) begin
|
||||
query_q <= query_hash;
|
||||
issue_base_q <= '0;
|
||||
returned_q <= 0;
|
||||
best_row_q <= TIE_BREAK_SENTINEL;
|
||||
best_score_q <= '0;
|
||||
`ifdef SIM_DEBUG
|
||||
score_debug_flat <= '0;
|
||||
`endif
|
||||
state_q <= S_SCAN;
|
||||
end
|
||||
end
|
||||
S_SCAN: begin
|
||||
if (issue_base_q + `LANES >= `NUM_ROWS) begin
|
||||
state_q <= S_DRAIN;
|
||||
end else begin
|
||||
issue_base_q <= issue_base_q + `LANES;
|
||||
end
|
||||
end
|
||||
S_DRAIN: begin
|
||||
if ((returned_q == (`NUM_ROWS / `LANES)) && !score_valid[0]) begin
|
||||
state_q <= S_DONE;
|
||||
end
|
||||
end
|
||||
S_DONE: begin
|
||||
if (result_ready) state_q <= S_IDLE;
|
||||
end
|
||||
default: state_q <= S_IDLE;
|
||||
endcase
|
||||
|
||||
if (score_valid[0]) begin
|
||||
returned_q <= returned_q + 1'b1;
|
||||
if ((batch_score > best_score_q) ||
|
||||
((batch_score == best_score_q) && (batch_row < best_row_q))) begin
|
||||
best_score_q <= batch_score;
|
||||
best_row_q <= batch_row;
|
||||
end
|
||||
`ifdef SIM_DEBUG
|
||||
for (int lane = 0; lane < `LANES; lane++) begin
|
||||
score_debug_flat[score_row[lane]*`SCORE_BITS +: `SCORE_BITS] <= lane_score[lane];
|
||||
end
|
||||
`endif
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
37
hw/rtl/noise_mask_grouped.sv
Normal file
37
hw/rtl/noise_mask_grouped.sv
Normal file
@@ -0,0 +1,37 @@
|
||||
`timescale 1ns / 1ps
|
||||
`include "cam_params.svh"
|
||||
|
||||
module noise_mask_grouped #(
|
||||
parameter int HASH_BITS = `HASH_BITS,
|
||||
parameter int NOISE_BITS = 8,
|
||||
parameter int NOISE_RATE_NUM = 1,
|
||||
parameter int NOISE_RATE_DEN = 100
|
||||
) (
|
||||
input logic [127:0] random_i,
|
||||
output logic [HASH_BITS-1:0] mask_o
|
||||
);
|
||||
localparam int GROUP_BITS = HASH_BITS / NOISE_BITS;
|
||||
localparam int BIT_INDEX_BITS = 6;
|
||||
localparam int SAMPLE_BITS = 8;
|
||||
localparam int GROUP_RAND_BITS = BIT_INDEX_BITS + SAMPLE_BITS;
|
||||
localparam int SAMPLE_RANGE = 1 << SAMPLE_BITS;
|
||||
localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
|
||||
|
||||
initial begin
|
||||
if (NOISE_BITS <= 0) $fatal(1, "NOISE_BITS must be > 0");
|
||||
if (HASH_BITS % NOISE_BITS != 0) $fatal(1, "HASH_BITS must be divisible by NOISE_BITS");
|
||||
if (GROUP_BITS != 64) $fatal(1, "GROUP_BITS must be 64 for 6-bit grouped noise");
|
||||
if (NOISE_BITS * GROUP_RAND_BITS > 128) $fatal(1, "NOISE_BITS consumes more than 128 random bits");
|
||||
if (NOISE_RATE_DEN <= 0) $fatal(1, "NOISE_RATE_DEN must be > 0");
|
||||
if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN) $fatal(1, "NOISE_RATE_NUM out of range");
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mask_o = '0;
|
||||
for (int i = 0; i < NOISE_BITS; i++) begin
|
||||
if (random_i[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
|
||||
mask_o[i * GROUP_BITS + random_i[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
72
hw/rtl/popcount_pipeline.sv
Normal file
72
hw/rtl/popcount_pipeline.sv
Normal file
@@ -0,0 +1,72 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module popcount_pipeline #(
|
||||
parameter int WIDTH = 512,
|
||||
parameter int ROW_BITS = 12,
|
||||
parameter int OUT_WIDTH = $clog2(WIDTH + 1)
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
input logic valid_i,
|
||||
input logic [ROW_BITS-1:0] row_i,
|
||||
input logic [WIDTH-1:0] bits_i,
|
||||
output logic valid_o,
|
||||
output logic [ROW_BITS-1:0] row_o,
|
||||
output logic [OUT_WIDTH-1:0] count_o
|
||||
);
|
||||
localparam int GROUP = 8;
|
||||
localparam int NUM_GROUPS = WIDTH / GROUP;
|
||||
localparam int GROUP_COUNT_WIDTH = $clog2(GROUP + 1);
|
||||
localparam int STAGE1_GROUPS = NUM_GROUPS / 4;
|
||||
|
||||
logic [GROUP_COUNT_WIDTH-1:0] group_counts [0:NUM_GROUPS-1];
|
||||
logic [OUT_WIDTH-1:0] partial_q [0:3];
|
||||
logic [OUT_WIDTH-1:0] sum_q;
|
||||
logic [ROW_BITS-1:0] row_s1_q, row_s2_q;
|
||||
logic valid_s1_q, valid_s2_q;
|
||||
logic [OUT_WIDTH-1:0] partial_comb [0:3];
|
||||
|
||||
always_comb begin
|
||||
for (int g = 0; g < NUM_GROUPS; g++) begin
|
||||
group_counts[g] = '0;
|
||||
for (int b = 0; b < GROUP; b++) begin
|
||||
group_counts[g] = group_counts[g] + bits_i[g*GROUP + b];
|
||||
end
|
||||
end
|
||||
|
||||
for (int p = 0; p < 4; p++) begin
|
||||
partial_comb[p] = '0;
|
||||
for (int g = 0; g < STAGE1_GROUPS; g++) begin
|
||||
partial_comb[p] = partial_comb[p] + group_counts[p*STAGE1_GROUPS + g];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
valid_s1_q <= 1'b0;
|
||||
valid_s2_q <= 1'b0;
|
||||
valid_o <= 1'b0;
|
||||
row_s1_q <= '0;
|
||||
row_s2_q <= '0;
|
||||
row_o <= '0;
|
||||
sum_q <= '0;
|
||||
count_o <= '0;
|
||||
for (int p = 0; p < 4; p++) partial_q[p] <= '0;
|
||||
end else begin
|
||||
valid_s1_q <= valid_i;
|
||||
row_s1_q <= row_i;
|
||||
for (int p = 0; p < 4; p++) begin
|
||||
partial_q[p] <= partial_comb[p];
|
||||
end
|
||||
|
||||
valid_s2_q <= valid_s1_q;
|
||||
row_s2_q <= row_s1_q;
|
||||
sum_q <= partial_q[0] + partial_q[1] + partial_q[2] + partial_q[3];
|
||||
|
||||
valid_o <= valid_s2_q;
|
||||
row_o <= row_s2_q;
|
||||
count_o <= sum_q;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Reference in New Issue
Block a user