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https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
refactor(cam): remove read noise from noise architecture (Phase 2)
- Make cam_read_noise a pass-through module, removing all noise injection logic - Switch write noise to use noise_mask_bernoulli instead of noise_mask_grouped - Add state machine to cam_write_noise for mask generation timing - Remove noise_mask_grouped.sv (no longer needed) - Remove read noise parameters from cam_noisy and cam_top - Update simulation and benchmark code to reflect read noise removal - Sync documentation to reflect Phase 2 architecture
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@@ -7,9 +7,5 @@ COCOTB_TEST_MODULES := tests.modules.cam_read_noise.test_cam_read_noise
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VERILOG_SOURCES := $(RTL_READ_NOISE)
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HASH_BITS ?= 512
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READ_NOISE_EN ?= 0
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READ_NOISE_RATE_NUM ?= 0
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READ_NOISE_RATE_DEN ?= 100
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READ_NOISE_BITS ?= $(shell echo $$(( $(HASH_BITS) / 64 )))
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include $(SIM_ROOT)/mk/cocotb-common.mk
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@@ -2,7 +2,7 @@ from __future__ import annotations
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.triggers import RisingEdge, Timer
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async def reset_read_noise(dut):
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@@ -38,11 +38,45 @@ async def read_noise_disabled_forwards_hashes_after_one_stage(dut):
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dut.row_ids_i.value = rows
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dut.lane_valid_i.value = all_lanes_valid
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dut.valid_i.value = 1
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await RisingEdge(dut.clk)
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await Timer(1, unit="step")
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await RisingEdge(dut.clk) # valid_o ← valid_i=1 internally
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await Timer(1, unit="step")
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dut.valid_i.value = 0
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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# One-stage pass-through: valid_o holds the latched value for this cycle
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assert int(dut.valid_o.value) == 1
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assert int(dut.hashes_noisy_o.value) == hashes
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assert int(dut.row_ids_o.value) == rows
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assert int(dut.lane_valid_o.value) == all_lanes_valid
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@cocotb.test()
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async def read_noise_enabled_still_forwards_hashes_unmodified(dut):
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"""With READ_NOISE_EN=1, the pass-through still forwards hashes unmodified."""
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cocotb.start_soon(Clock(dut.clk, 10, unit="ns").start())
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await reset_read_noise(dut)
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LANES = len(dut.lane_valid_i)
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ROW_BITS = len(dut.row_ids_i) // LANES
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HASH_BITS_PER_LANE = len(dut.hashes_i) // LANES
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all_lanes_valid = (1 << LANES) - 1
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hashes = 0
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rows = 0
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for lane in range(LANES):
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hashes |= (lane + 0x55) << (lane * HASH_BITS_PER_LANE)
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rows |= lane << (lane * ROW_BITS)
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dut.hashes_i.value = hashes
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dut.row_ids_i.value = rows
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dut.lane_valid_i.value = all_lanes_valid
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dut.valid_i.value = 1
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await Timer(1, unit="step")
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await RisingEdge(dut.clk) # valid_o ← valid_i=1 internally
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await Timer(1, unit="step")
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dut.valid_i.value = 0
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# One-stage pass-through: valid_o holds latched value from previous cycle
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assert int(dut.valid_o.value) == 1
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assert int(dut.hashes_noisy_o.value) == hashes
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assert int(dut.row_ids_o.value) == rows
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