feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility

- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring
- Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series
- Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis
- Add cam-synth just target for convenient invocation
- Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks)
  behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped
- Fix shadowed 'return' variable in random128 xorshift128 function

hw/rtl/noise/cam_read_noise.sv

@@ -27,9 +27,11 @@ module cam_read_noise #(
     logic [127:0] random_num [0:`LANES-1];
     logic [(`HASH_BITS)-1:0] mask [0:`LANES-1];
 
+    `ifndef SYNTHESIS
     initial begin
         if (READ_NOISE_SEED == 64'd0) $fatal(1, "READ_NOISE_SEED must be nonzero");
     end
+    `endif
 
     generate
         for (genvar lane = 0; lane < `LANES; lane++) begin : gen_lane_noise