feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility

- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring
- Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series
- Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis
- Add cam-synth just target for convenient invocation
- Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks)
  behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped
- Fix shadowed 'return' variable in random128 xorshift128 function

hw/rtl/core/cam_core_banked.sv

@@ -24,9 +24,11 @@ module cam_core_banked (
 
     assign wr_ready = 1'b1;
 
+    `ifndef SYNTHESIS
     initial begin
         if (`NUM_ROWS % `LANES != 0) $fatal(1, "NUM_ROWS must be divisible by LANES");
     end
+    `endif
 
     always_ff @(posedge clk) begin
         if (wr_valid) begin
@@ -44,9 +46,11 @@ module cam_core_banked (
             rd_valid_o      <= rd_valid_i;
             rd_lane_valid_o <= rd_valid_i ? {`LANES{1'b1}} : '0;
 
+            `ifndef SYNTHESIS
             if (rd_valid_i && ((rd_base_row_i % `LANES) != 0)) begin
                 $fatal(1, "rd_base_row_i must be LANES-aligned");
             end
+            `endif
 
             for (int lane = 0; lane < `LANES; lane++) begin
                 rd_row_ids_o[lane*`ROW_BITS +: `ROW_BITS] <= rd_base_row_i + lane[(`ROW_BITS)-1:0];