feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility

- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring
- Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series
- Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis
- Add cam-synth just target for convenient invocation
- Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks)
  behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped
- Fix shadowed 'return' variable in random128 xorshift128 function

hw/rtl/core/cam_core_banked.sv

@@ -24,9 +24,11 @@ module cam_core_banked (
 
     assign wr_ready = 1'b1;
 
+    `ifndef SYNTHESIS
     initial begin
         if (`NUM_ROWS % `LANES != 0) $fatal(1, "NUM_ROWS must be divisible by LANES");
     end
+    `endif
 
     always_ff @(posedge clk) begin
         if (wr_valid) begin
@@ -44,9 +46,11 @@ module cam_core_banked (
             rd_valid_o      <= rd_valid_i;
             rd_lane_valid_o <= rd_valid_i ? {`LANES{1'b1}} : '0;
 
+            `ifndef SYNTHESIS
             if (rd_valid_i && ((rd_base_row_i % `LANES) != 0)) begin
                 $fatal(1, "rd_base_row_i must be LANES-aligned");
             end
+            `endif
 
             for (int lane = 0; lane < `LANES; lane++) begin
                 rd_row_ids_o[lane*`ROW_BITS +: `ROW_BITS] <= rd_base_row_i + lane[(`ROW_BITS)-1:0];

hw/rtl/noise/cam_read_noise.sv

@@ -27,9 +27,11 @@ module cam_read_noise #(
     logic [127:0] random_num [0:`LANES-1];
     logic [(`HASH_BITS)-1:0] mask [0:`LANES-1];
 
+    `ifndef SYNTHESIS
     initial begin
         if (READ_NOISE_SEED == 64'd0) $fatal(1, "READ_NOISE_SEED must be nonzero");
     end
+    `endif
 
     generate
         for (genvar lane = 0; lane < `LANES; lane++) begin : gen_lane_noise

hw/rtl/noise/cam_write_noise.sv

@@ -44,9 +44,11 @@ module cam_write_noise #(
         .mask_o  (flip_mask)
     );
 
+    `ifndef SYNTHESIS
     initial begin
         if (WRITE_NOISE_SEED == 64'd0) $fatal(1, "WRITE_NOISE_SEED must be nonzero");
     end
+    `endif
 
     always_ff @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin

hw/rtl/noise/noise_mask_grouped.sv

@@ -17,6 +17,7 @@ module noise_mask_grouped #(
     localparam int SAMPLE_RANGE     = 1 << SAMPLE_BITS;
     localparam int THRESHOLD        = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
 
+    `ifndef SYNTHESIS
     initial begin
         if (NOISE_BITS <= 0) $fatal(1, "NOISE_BITS must be > 0");
         if (HASH_BITS % NOISE_BITS != 0) $fatal(1, "HASH_BITS must be divisible by NOISE_BITS");
@@ -25,6 +26,7 @@ module noise_mask_grouped #(
         if (NOISE_RATE_DEN <= 0) $fatal(1, "NOISE_RATE_DEN must be > 0");
         if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN) $fatal(1, "NOISE_RATE_NUM out of range");
     end
+    `endif
 
     always_comb begin
         mask_o = '0;

hw/rtl/random/random128.sv

@@ -42,7 +42,7 @@ module random128 (
             next_z = w;
             next_w = w ^ (w >> 19) ^ t ^ (t >> 8);
 
-            return {next_x, next_y, next_z, next_w};
+            xorshift128 = {next_x, next_y, next_z, next_w};
         end
     endfunction