feat(rtl): migrate CAM interface to handshake protocol with integrated noise generation

BREAKING CHANGE: CAM write and query interface replaced with standard valid/ready
handshake. wr_en/wr_row/wr_hash → wr_valid/wr_ready/wr_addr/write_hash.
External noise_mask_lanes_flat removed; noise generation now handled internally
by cam_noisy module with configurable rate via parameters.

- cam_top: add parameters (NOISE_EN, NOISE_RATE_NUM/DEN, NOISE_GEN/SAMPLE_BITS, NOISE_SEED)
- cam_top: replace cam_core with cam_noisy (integrated noise generation)
- match_engine: remove external noise_mask_lanes_flat input
- hw/sim: update Makefile with noise parameters and compile args
- hw/sim/model: add generate_write_flip_mask() and xorshift64() matching RTL behavior
- hw/sim/tests: adapt testbench to new handshake protocol

hw/sim/Makefile

@@ -9,6 +9,15 @@ NUM_ROWS ?= 512
 HASH_BITS ?= 512
 LANES ?= 16
 
+# Noise parameters
+NOISE_EN          ?= 1
+NOISE_RATE_NUM    ?= 1
+NOISE_RATE_DEN    ?= 100
+NOISE_GEN_BITS    ?= 8
+NOISE_SAMPLE_BITS ?= 8
+# NOISE_SEED cannot be overridden via Makefile due to Verilator -G quoting issues
+# with 64'h hex literals. To change the seed, edit the default in cam_noisy.sv.
+
 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
 
 COMPILE_ARGS += -Wall -Wno-fatal
@@ -16,6 +25,13 @@ COMPILE_ARGS += -I$(PWD)/../rtl
 COMPILE_ARGS += +define+SIM_DEBUG
 COMPILE_ARGS += $(EXTRA_DEFINES)
 
+# Noise parameter overrides via Verilator -G
+COMPILE_ARGS += -GNOISE_EN=$(NOISE_EN)
+COMPILE_ARGS += -GNOISE_RATE_NUM=$(NOISE_RATE_NUM)
+COMPILE_ARGS += -GNOISE_RATE_DEN=$(NOISE_RATE_DEN)
+COMPILE_ARGS += -GNOISE_GEN_BITS=$(NOISE_GEN_BITS)
+COMPILE_ARGS += -GNOISE_SAMPLE_BITS=$(NOISE_SAMPLE_BITS)
+
 # Cleaner terminal output
 export QUIET ?= 1
 export VERBOSE ?= 0
@@ -32,6 +48,7 @@ endif
 VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
 VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
+VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv
 VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv