SIM_ROOT := $(abspath ../../..)
RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
include $(SIM_ROOT)/mk/rtl-sources.mk

TOPLEVEL := cam_write_noise
COCOTB_TEST_MODULES := tests.modules.cam_write_noise.test_cam_write_noise
VERILOG_SOURCES := $(RTL_WRITE_NOISE)

HASH_BITS ?= 512
WRITE_NOISE_EN ?= 1
WRITE_NOISE_RATE_NUM ?= 1
WRITE_NOISE_RATE_DEN ?= 100
include $(SIM_ROOT)/mk/cocotb-common.mk
