SIM_ROOT := $(abspath ../../..)
RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
include $(SIM_ROOT)/mk/rtl-sources.mk

TOPLEVEL := cam_core_banked
COCOTB_TEST_MODULES := tests.modules.cam_core_banked.test_cam_core_banked
VERILOG_SOURCES := $(RTL_CAM_CORE_BANKED)

include $(SIM_ROOT)/mk/cocotb-common.mk
