31 lines
586 B
Verilog
31 lines
586 B
Verilog
// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module sync_ptr
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#(
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parameter ASIZE = 4
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)(
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input wire dest_clk,
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input wire dest_rst_n,
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input wire [ASIZE:0] src_ptr,
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output reg [ASIZE:0] dest_ptr
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);
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reg [ASIZE:0] ptr_x;
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always @(posedge dest_clk or negedge dest_rst_n) begin
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if (!dest_rst_n)
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{dest_ptr,ptr_x} <= 0;
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else
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{dest_ptr,ptr_x} <= {ptr_x,src_ptr};
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end
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endmodule
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`resetall
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