117 lines
3.9 KiB
Verilog
117 lines
3.9 KiB
Verilog
`timescale 1ns/1ps
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// 三通道图像合成一个RGB图像
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module chanels_to_RGB #(
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parameter IN_DEPTH = 12, // 输入图像的色深
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parameter OUT_DEPTH = 8, // 输出图像的色深
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parameter GAIN_RED = 120, // 红色增益系数(除以10^小数位数)
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parameter GAIN_GREEN = 50, // 绿色增益系数
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parameter GAIN_BLUE = 95, // 蓝色增益系数
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parameter DECIMAL = 2 // 小数位数
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) (
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input clk,
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input reset,
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input in_en,
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input [15:0] data_in [2:0], // 0:R 1:G 2:B
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// 输出相关
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input out_que, // 数据请求
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output out_en,
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output [3 * OUT_DEPTH - 1:0] data_out,
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// 颜色校正
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input wire color_correction
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);
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localparam READ_DATA = 0;
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localparam SEND_DATA = 1;
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reg [1:0] state, nextState;
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reg [31:0] data_cal [2:0]; // 用于保存运算结果，防止溢出
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reg fifo_en;
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reg [3 * OUT_DEPTH - 1:0] fifo_in; // 输入fifo中缓存
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wire fifo_empty, fifo_que;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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state <= READ_DATA;
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end
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else begin
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state <= nextState;
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end
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end
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always @(*) begin
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case (state)
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READ_DATA: nextState = (in_en) ? SEND_DATA : READ_DATA;
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SEND_DATA: nextState = READ_DATA;
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endcase
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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// 初始化
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data_cal[0] <= 0;
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data_cal[1] <= 0;
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data_cal[2] <= 0;
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fifo_en <= 0;
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fifo_in <= 0;
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end
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else begin
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case (state)
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READ_DATA: begin
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fifo_en <= 0;
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if (in_en) begin
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if (color_correction) begin
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data_cal[0] <= ( {16'b0, data_in[0] } >> (IN_DEPTH - OUT_DEPTH) ) * GAIN_RED / (10 ** DECIMAL);
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data_cal[1] <= ( {16'b0, data_in[1] } >> (IN_DEPTH - OUT_DEPTH) ) * GAIN_GREEN / (10 ** DECIMAL);
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data_cal[2] <= ( {16'b0, data_in[2] } >> (IN_DEPTH - OUT_DEPTH) ) * GAIN_BLUE / (10 ** DECIMAL);
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end
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else begin
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data_cal[0] <= ( {16'b0, data_in[0] } >> (IN_DEPTH - OUT_DEPTH) );
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data_cal[1] <= ( {16'b0, data_in[1] } >> (IN_DEPTH - OUT_DEPTH) );
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data_cal[2] <= ( {16'b0, data_in[2] } >> (IN_DEPTH - OUT_DEPTH) );
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end
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end
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end
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SEND_DATA: begin
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fifo_en <= 1;
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fifo_in <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0], data_cal[2][OUT_DEPTH - 1:0]};
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end
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endcase
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end
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end
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// 存在数据请求且FIFO不为空时，才发送数据
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assign fifo_que = (out_que && !fifo_empty) ? 1 : 0;
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SOFTFIFO #(
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.DATA_WIDTH_W(3 * OUT_DEPTH),
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.DATA_WIDTH_R(3 * OUT_DEPTH)
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) RGB_FIFO (
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.rst(reset), //asynchronous port,active hight
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.clkw(clk), //write clock
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.clkr(clk), //read clock
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.we(fifo_en), //write enable,active hight
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.di(fifo_in), //write data
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.re(fifo_que), //read enable,active hight
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.dout(data_out), //read data
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.valid(out_en), //read data valid flag
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/* verilator lint_off PINCONNECTEMPTY */
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.full_flag(), //fifo full flag
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.empty_flag(fifo_empty), //fifo empty flag
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/* verilator lint_off PINCONNECTEMPTY */
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.afull(), //fifo almost full flag
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/* verilator lint_off PINCONNECTEMPTY */
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.aempty(), //fifo almost empty flag
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/* verilator lint_off PINCONNECTEMPTY */
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.wrusedw(), //stored data number in fifo
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/* verilator lint_off PINCONNECTEMPTY */
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.rdusedw() //available data number for read
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);
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endmodule
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