96 lines
2.4 KiB
Verilog
96 lines
2.4 KiB
Verilog
module Crop #(
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parameter reg [15:0] IN_WIDTH = 1934,
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parameter reg [15:0] IN_HEIGHT = 1086,
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parameter reg [15:0] OFFSET_X = 8,
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parameter reg [15:0] OFFSET_Y = 4,
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parameter reg [15:0] OUT_WIDTH = 640,
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parameter reg [15:0] OUT_HEIGHT = 480,
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parameter reg [4:0] COLOR_DEPTH = 8
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) (
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input wire clk,
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input wire reset,
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input wire in_en,
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output wire out_ready,
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output wire out_receive,
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input wire [3 * COLOR_DEPTH - 1:0] in_data,
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input wire in_ready,
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input wire in_receive,
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output reg out_en,
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output reg [3 * COLOR_DEPTH - 1:0] out_data
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);
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reg [1:0] state, nextState;
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localparam reg [1:0] READ_DATA = 0;
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localparam reg [1:0] HANDLE_DATA = 1;
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localparam reg [1:0] SEND_DATA = 2;
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reg [15:0] cnt_x, cnt_y;
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reg [3 * COLOR_DEPTH - 1:0] data;
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wire is_valid;
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// 状态切换
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always @(posedge clk or posedge reset) begin
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if (reset) state <= READ_DATA;
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else state <= nextState;
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end
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// 下一状态更新
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always @(*) begin
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case (state)
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READ_DATA: nextState = in_en ? HANDLE_DATA : READ_DATA;
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HANDLE_DATA: nextState = SEND_DATA;
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SEND_DATA: nextState = (is_valid && !in_receive) ? SEND_DATA : READ_DATA;
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default: nextState = READ_DATA;
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endcase
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end
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assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
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assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) &&
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(OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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cnt_x <= 0;
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cnt_y <= 0;
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data <= 0;
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out_en <= 0;
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out_data <= 0;
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end else begin
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case (state)
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READ_DATA: begin
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if (in_en) begin
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data <= in_data;
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end
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end
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HANDLE_DATA: begin
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if (cnt_x >= IN_WIDTH - 1) begin
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cnt_x <= 0;
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cnt_y <= cnt_y + 1;
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end else begin
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cnt_x <= cnt_x + 1;
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end
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if (cnt_y >= IN_HEIGHT - 1) begin
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cnt_y <= 0;
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end
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end
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SEND_DATA: begin
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if (in_ready && !in_receive && is_valid) begin
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out_en <= 1;
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out_data <= data;
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end else out_en <= 0;
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end
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default: ;
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endcase
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end
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end
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endmodule
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