99 lines
2.1 KiB
Verilog
99 lines
2.1 KiB
Verilog
// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module async_fifo
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#(
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parameter DSIZE = 8,
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parameter ASIZE = 4,
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parameter FALLTHROUGH = "TRUE" // First word fall-through without latency
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)(
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input wire wclk,
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input wire wrst_n,
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input wire winc,
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input wire [DSIZE-1:0] wdata,
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output wire wfull,
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output wire awfull,
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input wire rclk,
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input wire rrst_n,
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input wire rinc,
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output wire [DSIZE-1:0] rdata,
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output wire rempty,
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output wire arempty
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);
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wire [ASIZE-1:0] waddr, raddr;
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wire [ASIZE :0] wptr, rptr, wq2_rptr, rq2_wptr;
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// The module synchronizing the read point
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// from read to write domain
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sync_r2w
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#(ASIZE)
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sync_r2w (
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.wq2_rptr (wq2_rptr),
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.rptr (rptr),
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.wclk (wclk),
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.wrst_n (wrst_n)
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);
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// The module synchronizing the write point
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// from write to read domain
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sync_w2r
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#(ASIZE)
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sync_w2r (
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.rq2_wptr (rq2_wptr),
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.wptr (wptr),
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.rclk (rclk),
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.rrst_n (rrst_n)
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);
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// The module handling the write requests
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wptr_full
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#(ASIZE)
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wptr_full (
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.awfull (awfull),
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.wfull (wfull),
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.waddr (waddr),
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.wptr (wptr),
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.wq2_rptr (wq2_rptr),
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.winc (winc),
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.wclk (wclk),
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.wrst_n (wrst_n)
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);
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// The DC-RAM
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fifomem
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#(DSIZE, ASIZE, FALLTHROUGH)
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fifomem (
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.rclken (rinc),
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.rclk (rclk),
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.rdata (rdata),
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.wdata (wdata),
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.waddr (waddr),
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.raddr (raddr),
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.wclken (winc),
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.wfull (wfull),
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.wclk (wclk)
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);
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// The module handling read requests
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rptr_empty
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#(ASIZE)
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rptr_empty (
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.arempty (arempty),
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.rempty (rempty),
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.raddr (raddr),
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.rptr (rptr),
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.rq2_wptr (rq2_wptr),
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.rinc (rinc),
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.rclk (rclk),
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.rrst_n (rrst_n)
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);
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endmodule
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`resetall
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