91 lines
2.4 KiB
Verilog
91 lines
2.4 KiB
Verilog
module crop #(
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parameter OFFSET_X = 8,
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parameter OFFSET_Y = 4,
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parameter OUT_WIDTH = 640,
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parameter OUT_HEIGHT = 480,
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parameter COLOR_DEPTH = 8
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) (
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input clk,
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input reset,
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input in_en,
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output reg in_que,
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input [3 * COLOR_DEPTH - 1:0] data_in,
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output reg out_en,
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output reg [3 * COLOR_DEPTH - 1:0] data_out
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);
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localparam READ_DATA = 0;
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localparam HANDLE_DATA = 1;
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localparam SEND_DATA = 2;
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reg [1:0] state, nextState;
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reg [11:0] cnt_x, cnt_y;
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reg [3 * COLOR_DEPTH - 1:0] data;
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// 状态切换
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always @(posedge clk or posedge reset) begin
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if (reset)
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state <= READ_DATA;
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else
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state <= nextState;
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end
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// 下一状态更新
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always @(*) begin
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case (state)
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READ_DATA: nextState = (in_que && in_en) ? HANDLE_DATA : READ_DATA;
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HANDLE_DATA: nextState = SEND_DATA;
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SEND_DATA: nextState = READ_DATA;
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endcase
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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cnt_x <= 0;
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cnt_y <= 0;
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data <= 0;
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end
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else begin
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case (state)
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READ_DATA: begin
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in_que <= 1;
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if (in_en) begin
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data <= data_in;
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in_que <= 0;
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end
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end
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HANDLE_DATA: begin
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if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
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if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
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out_en <= 1;
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end
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end
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if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
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cnt_x <= 0;
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if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
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cnt_y <= 0;
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end
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else begin
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cnt_y <= cnt_y + 1;
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end
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end
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else begin
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cnt_x <= cnt_x + 1;
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end
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end
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SEND_DATA: begin
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data_out <= data;
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out_en <= 0;
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end
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endcase
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end
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end
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endmodule
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