//Gowin SDPB IP�˷����ļ�
`timescale 1ns / 1ps
module Gowin_SDPB (
    input wire clka,
    input wire clkb,  //no use
    input wire reset,

    input wire cea,
    input wire ceb,

    input wire [10:0] ada,
    input wire [10:0] adb,

    input  wire [15:0] din,
    output reg  [15:0] dout,

    input wire oce  //no use
);

  reg [15:0] bram[2048];
  integer i;
  initial for (i = 0; i < 2048; i = i + 1) bram[i] = 0;

  always @(posedge clka) begin
    if (reset) for (i = 0; i < 2048; i = i + 1) bram[i] <= 0;
    else if (cea) bram[ada] <= din;
  end

  always @(posedge clka) begin
    if (reset) dout <= 0;
    else if (ceb) dout <= bram[adb];
  end


endmodule