diff --git a/.gitignore b/.gitignore
index 5ce9d4f..4e49483 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,4 +4,4 @@
 *.wlf
 *.mpf
 *.mti
-*/obj_dir/
\ No newline at end of file
+**/obj_dir/
\ No newline at end of file
diff --git a/Crop/crop.v b/Crop/crop.v
index 1911ea4..5b2aae0 100644
--- a/Crop/crop.v
+++ b/Crop/crop.v
@@ -11,16 +11,16 @@ module crop #(
     input reset,
 
     input in_en,
-    output reg in_que,
+    output in_que,
     input [3 * COLOR_DEPTH - 1:0] data_in,
 
-    output reg out_en,
+    output out_en,
     input out_que,
     output reg [3 * COLOR_DEPTH - 1:0] data_out
 );
-    wire fifo_en;
     wire fifo_full, fifo_empty;
     reg [11:0] cnt_x, cnt_y;
+    reg fifo_en;
 
     async_fifo #(
         .DSIZE(3 * COLOR_DEPTH),
@@ -34,10 +34,12 @@ module crop #(
         .winc(fifo_en),
         .wdata(data_in),
         .wfull(fifo_full),
+        .awfull(),
 
         .rinc(out_en),
         .rdata(data_out),
-        .rempty(fifo_empty)
+        .rempty(fifo_empty),
+        .arempty()
     );
 
     assign in_que = !fifo_full;
@@ -45,10 +47,7 @@ module crop #(
 
     always @(posedge clk or posedge reset) begin
         if (reset) begin
-            in_que <= 0;
-            out_en <= 0;
-            data_out <= 0;
-
+            fifo_en <= 0;
             cnt_x <= 0;
             cnt_y <= 0;
 
diff --git a/Merge/chanels_to_RGB.v b/Merge/chanels_to_RGB.v
index d5d0046..4ed4986 100644
--- a/Merge/chanels_to_RGB.v
+++ b/Merge/chanels_to_RGB.v
@@ -13,20 +13,23 @@ module chanels_to_RGB #(
 
     // 输出相关
     input data_que,                                 // 数据请求
-    output reg out_en,
-    output reg [3 * OUT_DEPTH - 1:0] data_out
+    output out_en,
+    output [3 * OUT_DEPTH - 1:0] data_out
 );
     reg [31:0] data_cal [2:0]; // 用于保存运算结果，防止溢出
     reg fifo_en;
-    wire [3 * OUT_DEPTH - 1:0] fifo_in; // 输入fifo中缓存
+    reg [3 * OUT_DEPTH - 1:0] fifo_in; // 输入fifo中缓存
     wire fifo_empty;
     // wire fifo_alempty;
 
     always @(posedge clk or posedge reset) begin
         if (reset) begin
             // 初始化
-            out_en <= 0;
-            data_out <= 0;
+            data_cal[0] <= 0;
+            data_cal[1] <= 0;
+            data_cal[2] <= 0;
+            fifo_en <= 0;
+            fifo_in <= 0;
         end
         else begin
             if (in_en) begin
@@ -55,10 +58,10 @@ module chanels_to_RGB #(
 
         .winc(fifo_en),
         .wdata(fifo_in),
-        // .wfull(),
-        // .awfull(),
+        .wfull(),
+        .awfull(),
         
-        // .arempty(fifo_alempty)
+        .arempty(),
         .rempty(fifo_empty),
         .rdata(data_out),
         .rinc(out_en)
diff --git a/RAM/RGB_to_RAM.v b/RAM/RGB_to_RAM.v
index 48d2f67..0aca79c 100644
--- a/RAM/RGB_to_RAM.v
+++ b/RAM/RGB_to_RAM.v
@@ -8,7 +8,7 @@ module RGB_to_RAM #(
     input reset,
 
     // 数据输入
-    output in_que,
+    output reg in_que,
     input in_en,
     input [3 * COLOR_DEPTH - 1:0] data_in,
 
@@ -39,10 +39,12 @@ module RGB_to_RAM #(
         .winc(in_en),
         .wdata(fifo_data),
         .wfull(fifo_full),
+        .awfull(),
 
         .rinc(write_en),
         .rdata(data_write),
-        .rempty(fifo_empty)
+        .rempty(fifo_empty),
+        .arempty()
     );
     
     // 当有数据请求且FIFO不为空时，输出数据
@@ -57,8 +59,6 @@ module RGB_to_RAM #(
 
     always @(posedge clk or posedge reset) begin
         if (reset) begin
-            write_en <= 0;
-            data_write <= 0;
             fifo_data <= 0;
             data_cache <= 0;
         end
diff --git a/isp.v b/isp.v
index f969c9a..4b8b9a0 100644
--- a/isp.v
+++ b/isp.v
@@ -27,9 +27,9 @@ module isp #(
     wire [15:0] im_red, im_green, im_blue;
 
     // 任意比例缩放图像
-    wire scale_in_en;
+    reg scale_in_en;
     wire scale_in_que;        // scaler 请求数据
-    wire [3 * COLOR_DEPTH - 1:0] scale_in_data;
+    reg [3 * COLOR_DEPTH - 1:0] scale_in_data;
 
     // 写入RAM
     wire RAM_in_en;
@@ -70,8 +70,8 @@ module isp #(
         .clk(clk),
         .reset(reset),
 
-        .in_en(scale_en),
-        .in_que(scale_que),
+        .in_en(scale_in_en),
+        .in_que(scale_in_que),
         .data_in(scale_in_data),
 
         .out_en(RAM_in_en),
@@ -83,9 +83,9 @@ module isp #(
         .clk(clk),
         .reset(reset),
 
-        .in_en(scale_in_en),
-        .in_que(scale_in_que),
-        .data_in(scale_in_data),
+        .in_en(RAM_in_en),
+        .in_que(RAM_in_que),
+        .data_in(RAM_in_data),
 
         .write_que(out_que),
         .write_en(out_en),