96 lines
2.8 KiB
Coq
96 lines
2.8 KiB
Coq
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//-----------------------------------------------------------------------------
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// Copyright 2017 Damien Pretet ThotIP
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// Copyright 2018 Julius Baxter
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//-----------------------------------------------------------------------------
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`timescale 1 ns / 1 ps
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`default_nettype none
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module fifomem_dp
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#(
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parameter DATASIZE = 8, // Memory data word width
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parameter ADDRSIZE = 4, // Number of mem address bits
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parameter FALLTHROUGH = "TRUE" // First word fall-through
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) (
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input wire a_clk,
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input wire [DATASIZE-1:0] a_wdata,
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output wire [DATASIZE-1:0] a_rdata,
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input wire [ADDRSIZE-1:0] a_addr,
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input wire a_rinc,
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input wire a_winc,
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input wire b_clk,
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input wire [DATASIZE-1:0] b_wdata,
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output wire [DATASIZE-1:0] b_rdata,
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input wire [ADDRSIZE-1:0] b_addr,
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input wire b_rinc,
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input wire b_winc
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);
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reg [DATASIZE-1:0] a_rdata_r;
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reg [DATASIZE-1:0] b_rdata_r;
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generate
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localparam DEPTH = 1<<ADDRSIZE;
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reg [DATASIZE-1:0] mem [0:DEPTH-1];
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if (FALLTHROUGH == "TRUE") begin : fallthrough
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always @(posedge a_clk)
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if (a_winc)
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mem[a_addr] <= a_wdata;
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assign a_rdata = mem[a_addr];
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always @(posedge b_clk)
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if (b_winc)
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mem[b_addr] <= b_wdata;
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assign b_rdata = mem[b_addr];
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end else begin : registered
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wire a_en = a_rinc | a_winc;
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always @(posedge a_clk)
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if (a_en) begin
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if (a_winc)
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mem[a_addr] <= a_wdata;
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a_rdata_r <= mem[a_addr];
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end
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assign a_rdata = a_rdata_r;
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wire b_en = b_rinc | b_winc;
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always @(posedge b_clk)
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if (b_en) begin
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if (b_winc)
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mem[b_addr] <= b_wdata;
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b_rdata_r <= mem[b_addr];
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end
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assign b_rdata = b_rdata_r;
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end // block: registered
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endgenerate
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endmodule
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`resetall
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