2024-05-10 21:41:47 +08:00
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// For std::unique_ptr
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#include <memory>
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// SystemC global header
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#include <systemc>
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// Include common routines
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#include <verilated.h>
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#include <verilated_vcd_sc.h>
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#include <sys/stat.h> // mkdir
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2024-05-14 21:25:59 +08:00
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// Include model header, generated from Verilating "isp.v"
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2024-05-10 21:41:47 +08:00
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#include "Visp.h"
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2024-05-15 16:35:17 +08:00
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// Handle file
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#include <fstream>
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#include <iostream>
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2024-05-18 18:56:32 +08:00
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#include "bmp.hpp"
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2024-05-15 16:35:17 +08:00
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2024-05-18 18:56:32 +08:00
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#define IN_WIDTH 1936
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#define IN_HEIGHT 1088
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2024-05-16 21:39:15 +08:00
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#define IN_SIZE (IN_WIDTH * IN_HEIGHT)
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2024-05-18 18:56:32 +08:00
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#define OUT_WIDTH 1920
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#define OUT_HEIGHT 1080
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2024-05-16 21:39:15 +08:00
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#define OUT_SIZE (OUT_WIDTH * OUT_HEIGHT)
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2024-05-15 16:35:17 +08:00
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using namespace std;
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2024-05-10 21:41:47 +08:00
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using namespace sc_core;
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using namespace sc_dt;
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2024-05-15 16:35:17 +08:00
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SC_MODULE (TB_ISP) {
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sc_in_clk clk;
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sc_in<bool> reset;
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sc_in<bool> data_que;
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sc_out<bool> data_en;
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sc_out<uint32_t> data_out[3];
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sc_in<bool> im_clk;
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sc_in<bool> im_en;
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sc_in<uint32_t> im_data;
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2024-05-16 21:39:15 +08:00
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sc_out<bool> is_done;
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2024-05-18 18:56:32 +08:00
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unique_ptr<uint16_t[]> image = make_unique<uint16_t[]>(IN_SIZE);
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2024-05-16 21:39:15 +08:00
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unique_ptr<uint32_t[]> out = make_unique<uint32_t[]>(OUT_SIZE);
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2024-05-15 16:35:17 +08:00
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SC_CTOR (TB_ISP) {
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SC_CTHREAD(send_Data, clk.pos());
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reset_signal_is(reset, true);
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SC_CTHREAD(read_Data, im_clk.pos());
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}
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void send_Data(void) {
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uint16_t pos_x = 0, pos_y = 0;
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while (true)
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{
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if (data_que.read() && pos_y < IN_HEIGHT - 2) {
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2024-05-15 16:35:17 +08:00
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data_en.write(1);
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2024-05-16 21:39:15 +08:00
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printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y, image[( pos_y + 0 ) * IN_WIDTH + pos_x]);
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printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y, image[( pos_y + 1 ) * IN_WIDTH + pos_x]);
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printf("x=%4d, y=%4d, data=0x%04x\n", pos_x, pos_y, image[( pos_y + 2 ) * IN_WIDTH + pos_x]);
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2024-05-15 16:35:17 +08:00
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2024-05-16 21:39:15 +08:00
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data_out[0].write(image[( pos_y + 0 ) * IN_WIDTH + pos_x]);
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data_out[1].write(image[( pos_y + 1 ) * IN_WIDTH + pos_x]);
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data_out[2].write(image[( pos_y + 2 ) * IN_WIDTH + pos_x]);
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2024-05-15 16:35:17 +08:00
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2024-05-16 17:15:25 +08:00
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wait(1);
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data_en.write(0);
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2024-05-18 18:56:32 +08:00
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if (++pos_x >= IN_WIDTH) {
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2024-05-15 16:35:17 +08:00
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pos_x = 0;
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pos_y++;
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}
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} else {
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data_en.write(0);
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}
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wait();
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}
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}
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void read_Data(void) {
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is_done.write(0);
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uint16_t pos_x = 0, pos_y = 0;
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uint32_t last_data = 0;
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uint16_t cnt = 0;
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while (true)
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{
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if (im_en.read()) {
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out[pos_y * OUT_WIDTH + pos_x] = im_data.read();
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if (pos_x++ >= OUT_WIDTH) {
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pos_x = 0;
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pos_y++;
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}
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}
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2024-05-16 21:39:15 +08:00
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if (last_data == im_data.read()) {
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cnt++;
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if (cnt >= 10000) {
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is_done.write(1);
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}
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} else {
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cnt = 0;
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}
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last_data = im_data.read();
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2024-05-15 16:35:17 +08:00
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wait();
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}
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}
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};
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2024-05-10 21:41:47 +08:00
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int sc_main(int argc, char* argv[]) {
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cout << "Get into sc_main" << endl;
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// Open image
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ifstream in_image;
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ofstream out_image;
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in_image.open("./transform/test.bin", ios::in | ios::binary);
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out_image.open("./transform/out.bin", ios::out | ios::binary);
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if (!in_image.is_open()) {
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cout << "Open image fail" << endl;
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exit(0);
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} else {
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cout << "Ready to sim" << endl;
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}
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// Read image
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auto buf = make_unique<uint8_t[]>(2 * IN_SIZE);
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in_image.read((char*)buf.get(), IN_SIZE * 2);
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in_image.close();
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// Reshape data
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auto image = make_unique<uint16_t[]>(IN_SIZE);
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uint32_t i = 0;
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for (int y = 0; y < IN_HEIGHT; y++) {
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for (int x = 0; x < IN_WIDTH; x++) {
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image[y * IN_WIDTH + x] = (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
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i += 2;
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}
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}
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cout << "Finish Reading data" << endl;
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2024-05-10 21:41:47 +08:00
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// This is a more complicated example, please also see the simpler examples/make_hello_c.
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// Create logs/ directory in case we have traces to put under it
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Verilated::mkdir("logs");
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// Set debug level, 0 is off, 9 is highest presently used
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// May be overridden by commandArgs argument parsing
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Verilated::debug(0);
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// Randomization reset policy
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// May be overridden by commandArgs argument parsing
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Verilated::randReset(2);
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// Before any evaluation, need to know to calculate those signals only used for tracing
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Verilated::traceEverOn(true);
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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// This needs to be called before you create any model
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Verilated::commandArgs(argc, argv);
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// General logfile
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std::ios::sync_with_stdio();
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// Define clocks
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sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
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// Define interconnect
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sc_signal<bool> reset;
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sc_signal<bool> data_en;
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sc_signal<bool> data_que;
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sc_signal<uint32_t> data_in[3];
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sc_signal<bool> out_clk;
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sc_signal<bool> out_en;
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sc_signal<uint32_t> data_out;
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2024-05-16 21:39:15 +08:00
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sc_signal<bool> flag_done;
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2024-05-10 21:41:47 +08:00
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2024-05-14 21:25:59 +08:00
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// Construct the Verilated model, from inside Visp.h
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// Using unique_ptr is similar to "Visp* isp = new Visp" then deleting at end
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const std::unique_ptr<Visp> isp{new Visp{"isp"}};
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// Attach Visp's signals to this upper model
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isp->clk(clk);
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isp->reset(reset);
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isp->data_en(data_en);
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isp->data_que(data_que);
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isp->data_in[0](data_in[0]);
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isp->data_in[1](data_in[1]);
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isp->data_in[2](data_in[2]);
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isp->out_clk(out_clk);
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isp->out_en(out_en);
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isp->data_out(data_out);
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// Construct testbench module
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TB_ISP tb_isp("tb_isp");
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tb_isp.clk(clk);
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tb_isp.reset(reset);
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tb_isp.data_que(data_que);
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tb_isp.data_en(data_en);
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tb_isp.data_out[0](data_in[0]);
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tb_isp.data_out[1](data_in[1]);
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tb_isp.data_out[2](data_in[2]);
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tb_isp.im_clk(out_clk);
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tb_isp.im_en(out_en);
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tb_isp.im_data(data_out);
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tb_isp.is_done(flag_done);
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tb_isp.image = move(image);
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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sc_start(SC_ZERO_TIME);
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// If verilator was invoked with --trace argument,
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// and if at run time passed the +trace argument, turn on tracing
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VerilatedVcdSc* tfp = nullptr;
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const char* flag = Verilated::commandArgsPlusMatch("trace");
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if (flag && 0 == std::strcmp(flag, "+trace")) {
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std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
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tfp = new VerilatedVcdSc;
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isp->trace(tfp, 99); // Trace 99 levels of hierarchy
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Verilated::mkdir("logs");
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tfp->open("logs/vlt_dump.vcd");
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}
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// Simulate until $finish
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while (!Verilated::gotFinish()) {
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// Flush the wave files each cycle so we can immediately see the output
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// Don't do this in "real" programs, do it in an abort() handler instead
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if (tfp) tfp->flush();
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// Apply inputs
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if (sc_time_stamp() < sc_time(10, SC_NS)) {
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reset.write(1); // Assert reset
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} else {
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reset.write(0); // Deassert reset
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2024-05-10 21:41:47 +08:00
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}
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2024-05-16 21:39:15 +08:00
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if (flag_done.read())
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break;
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2024-05-10 21:41:47 +08:00
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// Simulate 1ns
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sc_start(1, SC_NS);
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}
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// Final model cleanup
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2024-05-14 21:25:59 +08:00
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isp->final();
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2024-05-10 21:41:47 +08:00
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// Close trace if opened
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if (tfp) {
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tfp->close();
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tfp = nullptr;
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}
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2024-05-15 16:35:17 +08:00
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// Save output image
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cout << "Ready to save raw RGB image" << endl;
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// for (int y = 0; y < OUT_HEIGHT; y++)
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// for(int x = 0; x < OUT_WIDTH; x++)
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// out_image.write((const char *)&tb_isp.out[y * OUT_WIDTH + x], sizeof(tb_isp.out[0]));
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// out_image.close();
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// save to image
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uint8_t* data = new uint8_t[OUT_WIDTH * OUT_HEIGHT * 3]; // RGB24格式像素数据
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for (int32_t y = 0; y < OUT_HEIGHT; ++y) {
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for (int32_t x = 0; x < OUT_WIDTH; ++x) {
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int32_t index = (y * OUT_WIDTH + x) * 3;
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uint8_t red = ( tb_isp.out[y * OUT_WIDTH + x] & 0x00ff0000 ) >> 16;
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uint8_t green = ( tb_isp.out[y * OUT_WIDTH + x] & 0x0000ff00 ) >> 8;
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uint8_t blue = ( tb_isp.out[y * OUT_WIDTH + x] & 0x000000ff );
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out_image.write((const char *)&red, sizeof(red));
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out_image.write((const char *)&green, sizeof(green));
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out_image.write((const char *)&blue, sizeof(blue));
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printf("x=%4d, y=%4d, red=0x%02x, green=0x%02x, blue=0x%02x\n", x, y, red, green, blue);
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data[index + 0] = red; // R
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data[index + 1] = green; // G
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data[index + 2] = blue; // B
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}
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}
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write_bmp("test.bmp", data, OUT_WIDTH, OUT_HEIGHT);
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delete[] data;
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2024-05-10 21:41:47 +08:00
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// Return good completion status
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return 0;
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}
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