32 lines
573 B
Coq
32 lines
573 B
Coq
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module sync_w2r
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#(
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parameter ASIZE = 4
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)(
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input wire rclk,
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input wire rrst_n,
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output reg [ASIZE:0] rq2_wptr,
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input wire [ASIZE:0] wptr
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);
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reg [ASIZE:0] rq1_wptr;
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always @(posedge rclk or negedge rrst_n) begin
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if (!rrst_n)
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{rq2_wptr,rq1_wptr} <= 0;
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else
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{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
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end
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endmodule
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`resetall
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