51 lines
1.6 KiB
Systemverilog
51 lines
1.6 KiB
Systemverilog
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module frame_size_detect (
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input wire clk,
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input wire reset,
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input wire in_valid,
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input wire hstart,
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input wire fstart,
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input wire [15:0] h_pixel,
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input wire [15:0] v_pixel,
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output wire h_pixel_correct,
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output wire v_pixel_correct
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);
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reg [15:0] h_pixel_cnt, v_pixel_cnt;
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reg [3:0] h_pixel_match_times, v_pixel_match_times;
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assign h_pixel_correct = (h_pixel_match_times == 4'hF);
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assign v_pixel_correct = (v_pixel_match_times == 4'hF);
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always @(posedge clk) begin
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if(reset) h_pixel_cnt <= 0;
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else if(hstart & in_valid) h_pixel_cnt <= 0;
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else if(in_valid) h_pixel_cnt <= h_pixel_cnt + 1;
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else h_pixel_cnt <= h_pixel_cnt;
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end
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always @(posedge clk) begin
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if(reset) h_pixel_match_times <= 0;
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else if(hstart&in_valid) begin
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if(h_pixel_cnt == h_pixel - 1) h_pixel_match_times <= (h_pixel_match_times == 4'hF)?(h_pixel_match_times):(h_pixel_match_times + 1);
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else h_pixel_match_times <= 0;
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end else h_pixel_match_times <= h_pixel_match_times;
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end
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always @(posedge clk) begin
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if(reset) v_pixel_cnt <= 0;
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else if(fstart & in_valid) v_pixel_cnt <= 0;
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else if(hstart & in_valid) v_pixel_cnt <= v_pixel_cnt + 1;
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else v_pixel_cnt <= v_pixel_cnt;
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end
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always @(posedge clk) begin
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if(reset) v_pixel_match_times <= 0;
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else if(fstart & in_valid) begin
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if(v_pixel_cnt == v_pixel - 1) v_pixel_match_times <= (v_pixel_match_times == 4'hF)?(v_pixel_match_times):(v_pixel_match_times + 1);
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else v_pixel_match_times <= 0;
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end else v_pixel_match_times <= v_pixel_match_times;
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end
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endmodule
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