87 lines
1.8 KiB
Systemverilog
87 lines
1.8 KiB
Systemverilog
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`default_nettype none
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module Windows_tb ();
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// Related Paras
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parameter int CLK_PERIOD = 20;
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parameter int DATA_WIDTH = 16;
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parameter int WINDOWS_WIDTH = 5;
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parameter int DATA_LENGTH = 100;
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parameter int DATA_HEIGHT = 100;
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parameter int DATA_FLAMES = 3;
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// Related Ports
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bit clk = 1;
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bit rst = 0;
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logic in_valid = 0;
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logic [DATA_WIDTH - 1:0] in_data = 0;
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logic [7:0] in_user = 0;
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logic out_valid = 0;
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logic [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH ** 2] = '{default: 0};
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logic [7:0] out_user = 0;
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logic in_ready = 0;
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logic out_ready = 0;
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// Generate Clk
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always #(CLK_PERIOD / 2) clk = ~clk;
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// Reset Module
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initial begin
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rst = 1;
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#(10 * CLK_PERIOD);
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rst = 0;
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end
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// Send Data
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initial begin
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#(12 * CLK_PERIOD);
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in_ready = 1;
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#(3 * CLK_PERIOD);
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for (int f = 0; f < DATA_FLAMES; ++f) begin
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for (int j = 0; j < DATA_HEIGHT; ++j) begin
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for (int i = 0; i < DATA_LENGTH; ++i) begin
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in_user[1] = (j == 0 && i == 0) ? 1'b1 : 1'b0;
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in_user[0] = (i == 0) ? 1'b1 : 1'b0;
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in_data = j * DATA_LENGTH + i;
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in_valid = 1;
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#CLK_PERIOD;
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end
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end
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in_valid = 0;
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in_user = 0;
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#(50 * CLK_PERIOD);
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end
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$finish(100 * CLK_PERIOD);
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end
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// Connect to modules
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GSR GSR (.GSRI(1'b1));
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Windows #(
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.DATA_WIDTH (DATA_WIDTH),
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.WINDOWS_WIDTH (WINDOWS_WIDTH),
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.WINDOWS_ANCHOR_X(2),
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.WINDOWS_ANCHOR_Y(2)
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) Windows_inst (
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.clk (clk),
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.reset(rst),
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.in_valid(in_valid),
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.in_data (in_data),
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.in_user (in_user),
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.out_valid(out_valid),
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.out_data (out_data),
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.out_user (out_user),
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.in_ready (in_ready),
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.out_ready(out_ready)
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);
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endmodule
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