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SikongJueluo/FPGA_WebLab
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310 Commits 4 Branches 0 Tags
eb3a166079df020e7f707a44681552cc13bd7781
Commit Graph

8 Commits

Author SHA1 Message Date
SikongJueluo
822091243e fix: 修复前端捕获按钮的问题 2025-07-16 17:46:21 +08:00
SikongJueluo
8070e03496 feat: 添加强制捕获按钮 2025-07-16 16:23:40 +08:00
SikongJueluo
446da52515 feat: 实现逻辑分析仪的捕获功能 2025-07-15 20:37:25 +08:00
SikongJueluo
0410d14d3a feat: 完成逻辑分析仪前后端交互 2025-07-15 19:50:33 +08:00
SikongJueluo
ef76f3e9c7 refactor: 修改逻辑分析仪,使其直接使用manager进行管理 2025-07-15 18:49:37 +08:00
SikongJueluo
9f25391540 feat: 完成逻辑分析仪前端设计 2025-07-15 18:30:18 +08:00
SikongJueluo
4d6c06a0e0 feat: 添加逻辑分析仪 2025-07-14 16:07:37 +08:00
SikongJueluo
6068a10d67 feat: not finish logic analyzer ui 2025-07-14 12:15:53 +08:00
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