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SikongJueluo/FPGA_WebLab
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298 Commits 4 Branches 0 Tags
d30712d0f6e9c3cd00dc29efa38d2f48f3cf7278
Commit Graph

11 Commits

Author SHA1 Message Date
SikongJueluo
a56a65cc0d feat: 为获取idcode添加动画 2025-07-20 09:13:33 +08:00
SikongJueluo
9165c2e5f4 fix: 数字孪生的实验板不再需要设置开发板ip与端口 2025-07-16 16:47:52 +08:00
SikongJueluo
81f91b2b71 fix: boundary scan could not close and jtag scan failed 2025-05-20 20:31:52 +08:00
SikongJueluo
dc64a65702 feat: add power control 2025-05-20 19:11:29 +08:00
SikongJueluo
bea1c7e5ae feat: frontend add virtual matrix key 2025-05-20 17:09:57 +08:00
SikongJueluo
d754a881d7 feat: frontend add set jtag frequency 2025-05-19 21:18:22 +08:00
SikongJueluo
a6ac728cf1 fix: boundary scan could not save 2025-05-19 18:47:15 +08:00
SikongJueluo
ba6ec73b84 fix: frontend upload bitstream failed 2025-05-19 15:56:23 +08:00
SikongJueluo
5042bf8ce5 feat: frontend add boundary scan 2025-05-19 13:30:06 +08:00
SikongJueluo
c39f688115 fix: mother board reactive problem 2025-05-16 16:38:57 +08:00
SikongJueluo
1eded97c76 fix: remote update failed and template not found 2025-05-15 20:23:48 +08:00
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