This website requires JavaScript.
Explore
Help
Sign In
SikongJueluo
/
FPGA_WebLab
Archived
Watch
1
Star
0
Fork
0
You've already forked FPGA_WebLab
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
351
Commits
4
Branches
0
Tags
d2508f64840a5f28f972b0869aa6b2cda94e6b40
Commit Graph
4 Commits
Author
SHA1
Message
Date
alivender
e86cd5464e
add: 逻辑分析仪可设置采样频率
2025-08-04 14:31:58 +08:00
alivender
5c87204ef6
feat: 逻辑分析仪深度可用户输入自定义数字
2025-08-04 13:27:35 +08:00
alivender
6b701658d1
add: 为逻辑分析仪添加了深度、预存储深度、通道组设置
2025-07-31 13:14:23 +08:00
SikongJueluo
1273be7dee
feat: 完成logicanalyzer的api
2025-07-13 19:42:05 +08:00