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FPGA_WebLab
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9adc5295f870721a6011d6574ecbd9118ea1b07d
Commit Graph
4 Commits
Author
SHA1
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Date
alivender
6b701658d1
add: 为逻辑分析仪添加了深度、预存储深度、通道组设置
2025-07-31 13:14:23 +08:00
SikongJueluo
43e3cce048
fix: 更正逻辑分析仪频率
2025-07-16 15:27:53 +08:00
SikongJueluo
9f25391540
feat: 完成逻辑分析仪前端设计
2025-07-15 18:30:18 +08:00
SikongJueluo
c9fc6961fa
feat: 持续完善逻辑分析仪的界面
2025-07-14 16:42:30 +08:00