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SikongJueluo/FPGA_WebLab
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390 Commits 4 Branches 0 Tags
8e69c968913da4830e5913d036bb8b23969948b7
Commit Graph

6 Commits

Author SHA1 Message Date
SikongJueluo
a00cc84e48 fix: 修复数据库与SignalR无法连接的问题 2025-08-15 13:02:56 +08:00
SikongJueluo
b95a61c532 refactor: 重构数据库相关操作 2025-08-10 20:13:44 +08:00
alivender
e86cd5464e add: 逻辑分析仪可设置采样频率 2025-08-04 14:31:58 +08:00
alivender
5c87204ef6 feat: 逻辑分析仪深度可用户输入自定义数字 2025-08-04 13:27:35 +08:00
alivender
6b701658d1 add: 为逻辑分析仪添加了深度、预存储深度、通道组设置 2025-07-31 13:14:23 +08:00
SikongJueluo
1273be7dee feat: 完成logicanalyzer的api 2025-07-13 19:42:05 +08:00
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