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SikongJueluo/FPGA_WebLab
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342 Commits 4 Branches 0 Tags
51b39cee077f795b714624ea00edb0d472b90bb5
Commit Graph

8 Commits

Author SHA1 Message Date
alivender
6b701658d1 add: 为逻辑分析仪添加了深度、预存储深度、通道组设置 2025-07-31 13:14:23 +08:00
SikongJueluo
e3b769b24e feat: 添加嵌入式逻辑分析仪 2025-07-16 21:54:40 +08:00
alivender
8e19587a16 feat: 提交前端逻辑分析仪后台捕获;Camera现在可以以更高帧率运行 2025-07-16 21:14:23 +08:00
SikongJueluo
9f25391540 feat: 完成逻辑分析仪前端设计 2025-07-15 18:30:18 +08:00
SikongJueluo
c9fc6961fa feat: 持续完善逻辑分析仪的界面 2025-07-14 16:42:30 +08:00
SikongJueluo
4d6c06a0e0 feat: 添加逻辑分析仪 2025-07-14 16:07:37 +08:00
SikongJueluo
6068a10d67 feat: not finish logic analyzer ui 2025-07-14 12:15:53 +08:00
SikongJueluo
1273be7dee feat: 完成logicanalyzer的api 2025-07-13 19:42:05 +08:00
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