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SikongJueluo/FPGA_WebLab
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264 Commits 4 Branches 0 Tags
519094b3a096460c1351a460364a49d7aaedf1e5
Commit Graph

9 Commits

Author SHA1 Message Date
SikongJueluo
519094b3a0 fix: 修复前端逻辑分析仪数据配置错误导致无法应用配置的问题 2025-07-16 14:31:17 +08:00
SikongJueluo
446da52515 feat: 实现逻辑分析仪的捕获功能 2025-07-15 20:37:25 +08:00
SikongJueluo
0410d14d3a feat: 完成逻辑分析仪前后端交互 2025-07-15 19:50:33 +08:00
SikongJueluo
ef76f3e9c7 refactor: 修改逻辑分析仪,使其直接使用manager进行管理 2025-07-15 18:49:37 +08:00
SikongJueluo
9f25391540 feat: 完成逻辑分析仪前端设计 2025-07-15 18:30:18 +08:00
SikongJueluo
49cbdc51d9 fix: 修复多个外设无法认证的问题
refactor: 同时使用更加优雅的方式处理injection
2025-07-15 11:30:13 +08:00
SikongJueluo
c9fc6961fa feat: 持续完善逻辑分析仪的界面 2025-07-14 16:42:30 +08:00
SikongJueluo
4d6c06a0e0 feat: 添加逻辑分析仪 2025-07-14 16:07:37 +08:00
SikongJueluo
6068a10d67 feat: not finish logic analyzer ui 2025-07-14 12:15:53 +08:00
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