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FPGA_WebLab
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2adeca3b99c3e14e644a1e7ee6847a0120e98561
Commit Graph
4 Commits
Author
SHA1
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Date
alivender
6b701658d1
add: 为逻辑分析仪添加了深度、预存储深度、通道组设置
2025-07-31 13:14:23 +08:00
alivender
6dfd275091
add: 逻辑分析仪后端适配DDR存储功能
2025-07-29 20:38:31 +08:00
alivender
8e19587a16
feat: 提交前端逻辑分析仪后台捕获;Camera现在可以以更高帧率运行
2025-07-16 21:14:23 +08:00
SikongJueluo
1273be7dee
feat: 完成logicanalyzer的api
2025-07-13 19:42:05 +08:00