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SikongJueluo/FPGA_WebLab
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295 Commits 4 Branches 0 Tags
1fa944f3c7c894e1343fd57c0f3fc74792fdbb36
Commit Graph

8 Commits

Author SHA1 Message Date
SikongJueluo
e3b769b24e feat: 添加嵌入式逻辑分析仪 2025-07-16 21:54:40 +08:00
SikongJueluo
e38770a496 fix: 删除无用函数与信号,修复全屏bug 2025-07-13 16:00:49 +08:00
SikongJueluo
bad64bdfbd fix: 优化界面,解耦组件抽屉 2025-07-13 13:28:45 +08:00
SikongJueluo
28af2df093 feat: 优化工程页面的用户体验,包括删除一些不必要的元素,同时使用storage保存一些界面参数方便用户体验 2025-07-12 18:24:45 +08:00
SikongJueluo
f253a33c83 feat: 完善用户界面,添加绑定与解除绑定的功能 2025-07-12 17:46:23 +08:00
SikongJueluo
0fb0c4e395 feat: 后端添加获取空闲实验板,继续修改前端界面使其更加合理 2025-07-12 14:59:28 +08:00
SikongJueluo
fae07d9eae fix: postcss build failed 2025-07-11 17:48:33 +08:00
SikongJueluo
eedec80927 style: 重新调整结构 2025-07-11 17:31:49 +08:00
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