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FPGA_WebLab
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15c6eefe305eb8493f2e4304a3f91da59feb13e7
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3 Commits
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SikongJueluo
28af2df093
feat: 优化工程页面的用户体验,包括删除一些不必要的元素,同时使用storage保存一些界面参数方便用户体验
2025-07-12 18:24:45 +08:00
SikongJueluo
0fb0c4e395
feat: 后端添加获取空闲实验板,继续修改前端界面使其更加合理
2025-07-12 14:59:28 +08:00
SikongJueluo
eedec80927
style: 重新调整结构
2025-07-11 17:31:49 +08:00