SikongJueluo

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• Joined on 2024-03-24

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SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-17 15:49:38 +08:00

f5dd474ba0 feat: 完成实验板动态ip与动态mac

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-17 14:26:18 +08:00

fb13a5c484 fix: 修复删除过多东西导致无法读取数据的问题

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-17 14:11:28 +08:00

1053d71d29 fix: 由于解析错误导致的无法通信的问题

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-17 11:47:46 +08:00

56dcbf5caa fix: udpserver解析数据错误

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-17 11:23:48 +08:00

dfe279bf37 feat: 添加了端口占用检测，若被占用则不会启动

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 21:54:47 +08:00

e3b769b24e feat: 添加嵌入式逻辑分析仪

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 20:25:46 +08:00

d551cbe793 feat: 更新通信协议

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 17:46:28 +08:00

822091243e fix: 修复前端捕获按钮的问题

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 16:58:22 +08:00

bcee42d8c1 fix: 修复强制捕获的bug

9165c2e5f4 fix: 数字孪生的实验板不再需要设置开发板ip与端口

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SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 16:23:46 +08:00

8070e03496 feat: 添加强制捕获按钮

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 15:28:00 +08:00

43e3cce048 fix: 更正逻辑分析仪频率

bcdefb2779 feat: 简单实现debugger的通信

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SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 14:31:23 +08:00

519094b3a0 fix: 修复前端逻辑分析仪数据配置错误导致无法应用配置的问题

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 14:06:34 +08:00

57cf82b48f fix: 修改异步接受为同步接受

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 13:26:14 +08:00

b08b86dbbe fix: 使用C#自带的ping来刷新arp

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-16 12:23:19 +08:00

0cfbebf804 fix：重新使用sortedlist来保证udp接受数据的顺序

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 20:37:31 +08:00

446da52515 feat: 实现逻辑分析仪的捕获功能

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 20:03:29 +08:00

99dc7b52cc feat: 新增ARP刷新函数，并且在每次clearData后执行一次刷新

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 19:50:36 +08:00

0410d14d3a feat: 完成逻辑分析仪前后端交互

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 18:49:43 +08:00

ef76f3e9c7 refactor: 修改逻辑分析仪，使其直接使用manager进行管理

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 18:30:24 +08:00

9f25391540 feat: 完成逻辑分析仪前端设计