Logo
Explore Help
Sign In
SikongJueluo/FPGA_WebLab
1
0
Fork 0
You've already forked FPGA_WebLab
Code Issues Pull Requests Packages Projects Releases Wiki Activity
350 Commits 4 Branches 0 Tags
aff9da2a601e3e262d70db4e0d082ca46359a756
Commit Graph

9 Commits

Author SHA1 Message Date
alivender
5c87204ef6 feat: 逻辑分析仪深度可用户输入自定义数字 2025-08-04 13:27:35 +08:00
alivender
6b701658d1 add: 为逻辑分析仪添加了深度、预存储深度、通道组设置 2025-07-31 13:14:23 +08:00
SikongJueluo
e3b769b24e feat: 添加嵌入式逻辑分析仪 2025-07-16 21:54:40 +08:00
alivender
8e19587a16 feat: 提交前端逻辑分析仪后台捕获;Camera现在可以以更高帧率运行 2025-07-16 21:14:23 +08:00
SikongJueluo
9f25391540 feat: 完成逻辑分析仪前端设计 2025-07-15 18:30:18 +08:00
SikongJueluo
c9fc6961fa feat: 持续完善逻辑分析仪的界面 2025-07-14 16:42:30 +08:00
SikongJueluo
4d6c06a0e0 feat: 添加逻辑分析仪 2025-07-14 16:07:37 +08:00
SikongJueluo
6068a10d67 feat: not finish logic analyzer ui 2025-07-14 12:15:53 +08:00
SikongJueluo
1273be7dee feat: 完成logicanalyzer的api 2025-07-13 19:42:05 +08:00
Powered by Gitea Version: 1.24.6 Page: 83ms Template: 4ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API