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SikongJueluo/FPGA_WebLab
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400 Commits 4 Branches 0 Tags
7e53b805ae576fddbac045134e524f79caf3f9bc
Commit Graph

4 Commits

Author SHA1 Message Date
SikongJueluo
eea03f5bc8 feat: upload and download bitstream from the component of project view 2025-05-13 18:14:57 +08:00
SikongJueluo
20d4fa12d8 Server: finish jtag controller; Web: finish sibebar animation 2025-04-05 19:41:56 +08:00
SikongJueluo
d766e2ae6a add bun backend and add upload bitstream component 2025-03-18 17:28:21 +08:00
SikongJueluo
8b8eeb8207 init project and finish login page 2025-03-10 19:48:25 +08:00
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