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SikongJueluo/FPGA_WebLab
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144 Commits 4 Branches 0 Tags
6cf7ef02ac2e0372b97731406d3139439bbd9658
Commit Graph

10 Commits

Author SHA1 Message Date
SikongJueluo
f340c86a41 feat: add rect select but have some problems 2025-06-11 21:25:15 +08:00
SikongJueluo
a6ac728cf1 fix: boundary scan could not save 2025-05-19 18:47:15 +08:00
SikongJueluo
ba6ec73b84 fix: frontend upload bitstream failed 2025-05-19 15:56:23 +08:00
SikongJueluo
eea03f5bc8 feat: upload and download bitstream from the component of project view 2025-05-13 18:14:57 +08:00
SikongJueluo
020674a277 feat: change test view to basic jtag upload and download page 2025-05-09 21:44:51 +08:00
alivender
bc4f44ecaa feat: remake most of forntend 2025-04-26 19:59:35 +08:00
alivender
6526203981 feat: add right click keyboard match 2025-04-23 11:50:51 +08:00
SikongJueluo
292c73e757 finish sidebar router push 2025-04-05 20:49:50 +08:00
SikongJueluo
20d4fa12d8 Server: finish jtag controller; Web: finish sibebar animation 2025-04-05 19:41:56 +08:00
SikongJueluo
d766e2ae6a add bun backend and add upload bitstream component 2025-03-18 17:28:21 +08:00
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