SikongJueluo/FPGA_WebLab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

feat: 逻辑分析仪深度可用户输入自定义数字

Browse Source
This commit is contained in:
alivender
2025-08-04 13:27:35 +08:00
parent 51b39cee07
commit 5c87204ef6
5 changed files with 355 additions and 107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
server/src/Controllers/LogicAnalyzerController.cs
View File

@@ -259,7 +259,8 @@ public class LogicAnalyzerController : ControllerBase
{
try
{
if (capture_length < 0 || capture_length > 2048*32)
//DDR深度为 32'h01000000 - 32'h0FFFFFFF
if (capture_length < 0 || capture_length > 0x10000000 - 0x01000000)
return BadRequest("采样深度设置错误");
if (pre_capture_length < 0 || pre_capture_length >= capture_length)
return BadRequest("预采样深度必须小于捕获深度");

2
server/src/Peripherals/LogicAnalyzerClient.cs
View File

@@ -70,7 +70,7 @@ static class AnalyzerAddr
public const UInt32 DMA1_START_WRITE_ADDR = DMA1_BASE + 0x0000_0012;
public const UInt32 DMA1_END_WRITE_ADDR = DMA1_BASE + 0x0000_0013;
public const UInt32 DMA1_CAPTURE_CTRL_ADDR = DMA1_BASE + 0x0000_0014;
public const UInt32 STORE_OFFSET_ADDR = DDR_BASE + 0x0010_0000;
public const UInt32 STORE_OFFSET_ADDR = DDR_BASE + 0x0100_0000;
/// <summary>
/// 0x0100_0000 - 0x0100_03FF 只读 32位波形存储，得到的32位数据中低八位最先捕获，高八位最后捕获。<br/>